TFT Performance - Material Quality Correlation for a-Si:H Deposited at high Rates

1995 ◽  
Vol 377 ◽  
Author(s):  
S. Sherman ◽  
P-Y. Lu ◽  
R. A. Gottscho ◽  
S. Wagner
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Urbach Energy ◽  
Defect Density ◽  
High Rate ◽  
Linear Regime ◽  
Large Area ◽  
Film Properties ◽  
Deposition Power

ABSTRACTWe evaluated the characteristics of a-Si:H/a-SiNx:H thin film transistors (TFTs), and of separately deposited a-Si:H films, as functions of the a-Si:H deposition power in a high-rate, large-area, 40 MHz PE-CVD system. TFT performance and a-Si:H film properties improve with decreasing power density and deposition rate. However, low defect density a-Si:H material was deposited at rates as high as 1500 Å/min. TFTs with gate nitride deposited at 1000 A/min show excellent I-V characteristics when the a-Si:H deposition power is low enough. The TFT electron mobility in the linear regime correlates well with the Urbach energy of the a-Si:H films, suggesting that the quality of the a-Si: H controls the performance of our TFTs.

Improved Mobility and Bias Stability of Thin Film Transistors Using the Double-Layer a-InGaZnO/a-InGaZnO:N Channel

2016 ◽  
Vol 16 (4) ◽  
pp. 3659-3663
Author(s):  
H Yu ◽  
L Zhang ◽  
X. H Li ◽  
H. Y Xu ◽  
Y. C Liu
Keyword(s):  
Thin Film ◽  
Double Layer ◽  
Thin Film Transistors ◽  
Carrier Transport ◽  
Single Layer ◽  
Channel Structure ◽  
Gate Insulator ◽  
Large Area ◽  
Threshold Voltage Shift ◽  
High Carrier

The amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) were demonstrated based on a double-layer channel structure, where the channel is composed of an ultrathin nitrogenated a-IGZO (a-IGZO:N) layer and an undoped a-IGZO layer. The double-layer channel device showed higher saturation mobility and lower threshold-voltage shift (5.74 cm2/Vs, 2.6 V) compared to its single-layer counterpart (0.17 cm2/Vs, 7.23 V). The improvement can be attributed to three aspects: (1) improved carrier transport properties of the channel by the a-IGZO:N layer with high carrier mobility and the a-IGZO layer with high carrier concentration, (2) reduced interfacial trap density between the active channel and the gate insulator, and (3) higher surface flatness of the double-layer channel. Our study reveals key insights into double-layer channel, involving selecting more suitable electrical property for back-channel layer and more suitable interface modification for active layer. Meanwhile, room temperature fabrication amorphous TFTs offer certain advantages on better flexibility and higher uniformity over a large area.

Large-area and highly uniform carbon nanotube film for high-performance thin film transistors

Nano Research ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 4356-4367 ◽  
Author(s):  
Guodong Dong ◽  
Jie Zhao ◽  
Lijun Shen ◽  
Jiye Xia ◽  
Hu Meng ◽  
...  
Keyword(s):  
Thin Film ◽  
Carbon Nanotube ◽  
Thin Film Transistors ◽  
High Performance ◽  
Large Area ◽  
Carbon Nanotube Film ◽  
Highly Uniform

Development of Top-Gate Nanocrystalline Si:H Thin Film Transistors

2004 ◽  
Vol 808 ◽  
Author(s):  
Jarrod McDonald ◽  
Vikram L. Dalal ◽  
Max Noack
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Breakdown Strength ◽  
Defect Density ◽  
Hydrogen Plasma ◽  
Interface State ◽  
Nitride Layer ◽  
High Ratio ◽  
X Ray Diffraction ◽  
X Ray

ABSTRACTWe report on the growth and fabrication of top gate thin film transistors at low temperatures in nanocrystalline Si:H. The nanocrystalline Si:H was deposited using a VHF-PECVD plasma process at 45 MHz in a diode reactor. The material was deposited from a mixture of silane and hydrogen at a temperature of 250-300°C. Higher temperatures resulted in a loss of hydrogen from the material. The properties of the nanocrystalline Si:H were studied using x-ray diffraction and Raman spectroscopy. The material showed a high ratio (3.8) between the crystalline and amorphous peaks in the Raman spectrum. X-ray diffraction data showed the films to be predominantly oriented in <111> direction, and the grain size estimated from Scherer's formula was in the range of 12-15 nm. The doping of the material could be changed by introducing ppm levels of Boron or Phosphorus. The as-grown material was generally n type. By adding controlled amounts of B, the material could be made p type. The devices made were n-channel MISFET's with p body. The n+ source and drain layers were made from amorphous Si:H. A systematic investigation of the appropriate oxide/nitride layer to be used was undertaken. The nitride layers were grown at 250-300°C using mixtures of silane and ammonia, with a high degree of dilution by helium. The presence of helium dilution, along with post-deposition passivation by a hydrogen plasma, was found to produce reproducible, low interface defect density nitride materials. Interface state densities were measured using capacitance spectroscopy at different frequencies and temperatures and found to be in the range of 4.5x1011/cm2-eV. The breakdown strength of the nitride was measured and found to be 4 MV/cm. Proof-of-concept TFT devices were fabricated using reactive ion etching. The threshold voltage was in the range of 13-15 V, and the on/off ratio was in the range of 103.

Large-Area Doping for Poly-Si Thin Film Transistors Using Bucket Ion Source with an RF Plasma Cathode

1991 ◽  
Vol 30 (Part 2, No. 4B) ◽  
pp. L772-L774
Author(s):  
Genshiro Kawachi ◽  
Takashi Aoyama ◽  
Takaya Suzuki ◽  
Yasunori Ohno ◽  
Akio Mimura ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Ion Source ◽  
Rf Plasma ◽  
Large Area ◽  
Plasma Cathode ◽  
Si Thin Film

Large Area Electronics for Flat Panel Imagers Progress and Challenges

2002 ◽  
Vol 715 ◽  
Author(s):  
J.P. Lu ◽  
K. Van Schuylenbergh ◽  
J. Ho ◽  
Y. Wang ◽  
J. B. Boyce ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Laser Annealing ◽  
Thin Film Transistor ◽  
Large Area ◽  
Flat Panel ◽  
Excimer Laser Annealing ◽  
And Performance ◽  
Flat Panel Imagers ◽  
Large Area Electronics

AbstractThe technology of large area electronics has made significant progress in recent years because of the fast maturing excimer laser annealing process. The new thin film transistors based on laser processed poly silicon provide unprecedented performance over the traditional thin film transistors using amorphous silicon. They open up the possibility of building flat panel displays and imagers with higher integration and performance. In this paper, we will review the progress of poly-Si thin film transistor technology with emphasis on imager applications. We also discuss the challenges of future improvement of flat panel imagers based on this technology.

Chemical durability engineering of solution-processed oxide thin films and its application in chemically-robust patterned oxide thin-film transistors

2017 ◽  
Vol 5 (2) ◽  
pp. 339-349 ◽  
Author(s):  
Sung Woon Cho ◽  
Da Eun Kim ◽  
Won Jun Kang ◽  
Bora Kim ◽  
Dea Ho Yoon ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Thermal Treatment ◽  
Thin Film Transistors ◽  
Oxide Films ◽  
Chemical Durability ◽  
Oxide Thin Film ◽  
Large Area ◽  
Solution Processed ◽  
Circuit Integration

The chemical durability of solution-processed oxide films was engineered via Sn-incorporation and thermal-treatment, which was applied for large-area TFT circuit integration.

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