Trapping Behavior of Thin Siliconoxynitride Layers Prepared by Rapid Thermal Processing

1996 ◽  
Vol 428 ◽  
Author(s):  
R. Beyer ◽  
H. Burghardt ◽  
R. Reich ◽  
E. Thomas ◽  
D. Grambole ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Interface State ◽  
Oxidation States ◽  
Nuclear Reaction Analysis ◽  
Depth Profiles ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

AbstractSiliconoxynitride layers with thicknesses between 5 and 10 nm were grown on (100) oriented silicon by rapid thermal processing (RTP) using either N2O or NH3 as nitridant. In order to study the trapping behaviour at the interface and in the insulator bulk, capacitance-voltage (CV) and current-voltage (IV) measurements have been performed combined with different magnitudes of Fowler-Nordheim stress. In addition, Deep Level Transient Spectroscopy (DLTS) has been applied for interface state detection. Auger Electron Spectroscopy (AES) has been used to obtain depth profiles for Si, N, O and C. The deconvolution of the AES signal displays significant peak contributions related to intermedium oxidation states. Nuclear Reaction Analysis (NRA) was successfully applied for hydrogen detection in buried SiOxNy thin films.

Ion Implantation-Induced Defects and the Influence of Titanium Silicidation

1998 ◽  
Vol 510 ◽  
Author(s):  
D.Z. Chi ◽  
S. Ashok ◽  
D. Theodore
Keyword(s):  
Ion Implantation ◽  
Thermal Processing ◽  
Thermal Evolution ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Current Voltage ◽  
Transient Spectroscopy ◽  
Thermal Signature ◽  
P Type ◽  
Induced Defects

AbstractThermal evolution of ion implantation-induced defects and the influence of concurrent titanium silicidation in pre-amorphized p-type Si (implanted with 25 KeV, 1016 cm2Si+) under rapid thermal processing (RTP) have been investigated. Presence of implantation-induced electrically active defects has been confirmed by current-voltage (IV) and deep level transient spectroscopy (DLTS) measurements. DLTS characterization results show that the evolution of electrically active defects in the Si implanted samples under RTP depend critically on the RTP temperature: Hole traps HI (0.33 eV) and H4 (0.47 eV) appear after the highest temperature (950 °C) anneal, while a single trap H3 (0.26 eV) shows up at lower anneal temperatures (≤ 900 °C). The thermal signature of H4 defect is very similar to that of the iron interstitial while those of HI and H3 levels appear to originate from some interstitial-related defects, possibly complexes. A most interesting finding is that the above interstitial related defects can be eliminated completely with Ti silicidation, apparently a result of vacancy injection. However the silicidation process itself introduces a new H2 (0.30 eV) level, albeit at much lower concentration. This same H2 level is also seen in unimplanted samples under RTP. The paper will present details of defect evolution under various conditions of RTP for samples with and without the self-implantation and silicidation.

Rapid-Thermal-Processing Induced Deep Level Traps and their Spatial Distribution in MBE GaAs

1987 ◽  
Vol 92 ◽  
Author(s):  
Akio Kitagawa ◽  
Yutaka Tokuda ◽  
Akira Usami ◽  
Takao Wada ◽  
Hiroyuki kano
Keyword(s):  
Thermal Processing ◽  
Deep Level Transient Spectroscopy ◽  
Molecular Beam ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Spatial Variations ◽  
Molecular Beam Epitaxial ◽  
Gaas Films ◽  
Si Doped ◽  
Transient Spectroscopy

ABSTRACTRapid thermal processing (RTP) using halogen lamps for a Si-doped molecular beam epitaxial (MBE) n-GaAs layers was investigated by deep level transient spectroscopy. RTP was performed at 700°C, 800°C and 900°C for 6 s. Two electron traps NI ( Ec-0.5-0.7eV) and EL2 (Ec - 0.82 eV) are produced by RTP at 800 and 900°C.The peculiar spatial variations of the Nl and EL2 concentration across the MBE GaAs films are observed. The larger concentrations of the trap N1 and EL2 are observed near the edge of the samples, and the minima of N1 and EL2 concentration lie between the center and the edge of the sample. It seems that these spatial variations of N1 and EL2 concentration are consistent with that of the thermal stress induced by RTP. Furthermore, the EL2 concentration near the edge of the sample is suppressed by the contact with the GaAs pieces on the edge around the sample during RTP.

Electronic Properties of ZnO/Si Heterojunction Prepared by ALD.

2011 ◽  
Vol 178-179 ◽  
pp. 130-135 ◽  
Author(s):  
Vincent Quemener ◽  
Mari Alnes ◽  
Lasse Vines ◽  
Ola Nilsen ◽  
Helmer Fjellvåg ◽  
...  
Keyword(s):  
Electronic Properties ◽  
Deep Level ◽  
Atomic Layer ◽  
Substantial Improvement ◽  
Conduction Band Edge ◽  
Energy Position ◽  
Layer Deposition ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

ZnO/n-Si and ZnO/p-Si heterostructures were prepared by Atomic layer deposition (ALD) and the electronic properties have been investigated by Current-Voltage (I-V), Capacitance-Voltage (C-V) and Deep level transient spectroscopy (DLTS) measurements. DLTS measurements show two dominants electron traps at the interface of the ZnO/n-Si junction with energy position at 0.07 eV and 0.15 eV below the conduction band edge, labelled E(0.07) and E(0.15), respectively, and no electrically active defects at the interface of the ZnO/p-Si junction. E(0.07) is reduced by annealing up to 400°C while E(0.15) is created at 500°C. The best heterostructure is found after heat treatment at 400°C with a substantial improvement of the current rectification for ZnO/n-Si and the formation of Ohmic contact on ZnO/p-Si. A reduction of the interface defects correlates with an improvement of the crystal structure of the ZnO film with a preferred orientation along the c-axis.

Effects of Rapid Thermal Processing on SiO2/GaAs Interfaces

1988 ◽  
Vol 126 ◽  
Author(s):  
Yutaka Tokuda ◽  
Masayuki Katayama ◽  
Nobuo Ando ◽  
Akio Kitagawa ◽  
Akira Usami ◽  
...  
Keyword(s):  
Outer Surface ◽  
Photoelectron Spectroscopy ◽  
Thermal Processing ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Rf Sputtering ◽  
Electron Traps ◽  
Conventional Furnace ◽  
Pile Up ◽  
Transient Spectroscopy

ABSTRACTEffects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been investigated with Auger electron spectroscopy and X-ray photoelectron spectroscopy. SiO2 films of 100, 175, 200 and 1250 nm thickness have been deposited on liquid encapsulated Czochralski-grown (100) n-type GaAs wafers by the RF sputtering method. RTP has been performed at 800°C for 6 s. For comparison, conventional furnace processing (CFP) has also been performed at 800°C for 20 min for 200-nm-thick SiO2/GaAs. The Ga is observed on the outer SiO2 surface for RTP samples as well as CFP samples. This indicates that the outdiffusion of Ga occurs after only 6 s at 800°C even through 1250-nm-thick SiO2 films. The depth profile of Ga reveals the pile-up of Ga on the outer SiO2 surface for both RTP and CFP samples. The amount of Ga on the outer surface gradually increases in the thickness range 1250 to 175 nm. The As is also observed on the outer surface. The amount of Ga and As on the outer surface rapidly increases at 100 nm thickness. Electron traps in RTP samples have been studied with deep-level transient spectroscopy. Different electron traps are produced in GaAs by RTP between 100-nm- and 200-nm-thick SiO2/GaAs. It is thought that the production of different traps by RTP is related to the amount of Ga and As loss through SiO2 films from GaAs.

Electronic Properties Of Defects Formed In n-Si During Sputter-Etching In An Ar Plasma

1996 ◽  
Vol 442 ◽  
Author(s):  
P. N. K. Deenapanray ◽  
F. D. Auret ◽  
C. Schutte ◽  
G. Myburg ◽  
W. E. Meyer ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Deep Level ◽  
High Energy ◽  
Barrier Heights ◽  
Opposite Trend ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Ar Plasma ◽  
Transient Spectroscopy ◽  
Sputter Etching

AbstractWe have employed current-voltage (IV), capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) techniques to characterise the defects induced in n-Si during RF sputter-etching in an Ar plasma. The reverse leakage current, at a bias of 1 V, of the Schottky barrier diodes fabricated on the etched samples was found to decrease with etch time reaching a minimum at 6 minutes and thereafter increased. The barrier heights followed the opposite trend. The plasma processing introduced six prominent deep levels below the conduction band of the substrate. A comparison with the defects induced during high energy (MeV) alpha-particle, proton and electron irradiation of the same material revealed that plasma-etching created the VO- and VP-centres, and V2-10. Some of the remaining sputter-etching-induced (SEI) defects have tentatively been related to those formed during either 1 keV He- or Ar-ion bombardment.

Characterization of CdS–CuInSe2 solar cells by current–voltage, capacitance–voltage, and capacitance-transient measurements

1987 ◽  
Vol 65 (8) ◽  
pp. 966-971 ◽  
Author(s):  
N. Christoforou ◽  
J. D. Leslie ◽  
S. Damaskinos
Keyword(s):  
Solar Cells ◽  
Deep Level ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Carrier Trap ◽  
Transient Spectroscopy ◽  
Increasing Temperature ◽  
P Type ◽  
Capacitance Transient ◽  
Transient Measurements

CdS–CuInSe2 solar cells, which have an efficiency of 9%, have been studied by current–voltage, capacitance–voltage, and capacitance-transient measurements over the temperature range 90–380 K. Deep-level transient spectroscopy analysis of the capacitance transient measurements reveals one majority carrier trap with an activation energy of 0.70 ± 0.02 eV. Although the present experiment cannot establish definitely if the trap is in the CdS or CuInSe2 layer, arguments are presented that it is a hole trap in the p-type CuInSe2 layer. Current–voltage measurements indicate a reversible increase in the reverse-bias leakage current with increasing temperature above 300 K. Evidence is presented that suggests that the rectifying barrier height in the CdS–CuInSe2 solar cell decreases rapidly with temperature above 300 K. Capacitance versus voltage measurements suggest that the depiction layer being studied is primarily in the CuInSe2, but the temperature dependence of the ionized charge concentration N(x) cannot be totally explained although one possible cause is suggested.

DLTS Studies of Al Diffused n-Si

2010 ◽  
Vol 442 ◽  
pp. 393-397
Author(s):  
S. Siddique ◽  
M.M. Asim ◽  
F. Saleemi ◽  
S. Naseem
Keyword(s):  
Cross Section ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Dlts Spectrum ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Junction Formation ◽  
Transient Spectroscopy ◽  
Phosphorus Doped ◽  
Si Wafer

We have studied the electrical properties of Si p-n junction diodes by deep level transient spectroscopy (DLTS) measurements. The p-n junctions were developed on a Phosphorus doped Si by depositing Al and annealing at various temperatures. In order to confirm junction formation, current-voltage and capacitance-voltage measurements were made. Two deep levels at Ec-0.17 eV (E1) and Ec-0.44 eV (E2) were observed in the DLTS spectrum. These traps have been characterized by their capture cross-section, activation energy level and trap density. On the basis of these parameters, level E1 can be assigned as V-O complex and E2 as P-V complex. These traps are related to the growth of n-Si wafer and not due to Al diffusion.

Material and Electrical Properties of Gate Dielectrics Grown by Rapid Thermal Processing

1985 ◽  
Vol 52 ◽  
Author(s):  
J. Nulman ◽  
J. P. Krusius ◽  
P. Renteln
Keyword(s):  
Silicon Dioxide ◽  
Thermal Processing ◽  
Material Characterization ◽  
Gate Dielectrics ◽  
Rapid Thermal Processing ◽  
Pure Oxygen ◽  
Dielectric Films ◽  
Electrical Characteristics ◽  
Current Voltage ◽  
Capacitance Voltage

ABSTRACTThe material and electrical characteristics of silicon dielectric films prepared via Rapid Thermal Processing (RTP) are described. A commercial RTP system with heat provided by tungsten-halogen lamps was used. Silicon dioxide films were grown in pure oxygen and in oxygen with 4% hydrogen chloride ambients. As grown films were either annealed in a nitrogen ambient or nitrided in an ammonia ambient. Film thickness ranges from 4 to 70 nm for RTP times from 0 to 300 s at 1150 C. Current-voltage and capacitance-voltage methods were used for electrical characteristics. Ellipsometry, Auger and TEM were used for material characterization.

Deep-Level Transient Spectroscopy Studies of Rapid Thermal Processed GaAs with Sio2 Encapsulant

1989 ◽  
Vol 146 ◽  
Author(s):  
Masayuki Katayama ◽  
Yutaka Tokuda ◽  
Nobuo Ando ◽  
Akio Kitagawa ◽  
Akira Usami ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Thermal Processing ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
X Ray ◽  
Pile Up ◽  
Capacitance Voltage ◽  
Transient Spectroscopy ◽  
Spectroscopy Studies ◽  
Interface Effects

ABSTRACTEffects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been studied with X-ray photoelectron spectroscopy, capacitance-voltage measurements and deep-level transient spectroscopy. SiO2 films of 50, 200 and 1250 nim thickness have been deposited on GaAs. RTP has been performed at 760 and 910°C for 9 s. The rapid diffusion of Ga through the SiO2 film occurs, and the As loss and the formation of the As layer near the interface are observed. The decrease of the carrier concentration occurs in all RTP samples. Five electron traps EAI (Ec – 0.27 eV), EA2 (Ec – 0.32 eV), EA3 (Ec – 0.47 eV), EA4 (Ec – 0.58 eV) and EL2 (Ec – 0.78 eV) are produced by RTP. It is considered that the production of the trap EL2 is closely related to the Ga outdiffusion into the SiO2 film and the As indiffusion from the pile-up of elemental As near the interface. Effects of SiO2 film thickness on RTP-SiO2/GaAs are also reported.

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