Electronic Properties of ZnO/Si Heterojunction Prepared by ALD.

2011 ◽  
Vol 178-179 ◽  
pp. 130-135 ◽  
Author(s):  
Vincent Quemener ◽  
Mari Alnes ◽  
Lasse Vines ◽  
Ola Nilsen ◽  
Helmer Fjellvåg ◽  
...  
Keyword(s):  
Electronic Properties ◽  
Deep Level ◽  
Atomic Layer ◽  
Substantial Improvement ◽  
Conduction Band Edge ◽  
Energy Position ◽  
Layer Deposition ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

ZnO/n-Si and ZnO/p-Si heterostructures were prepared by Atomic layer deposition (ALD) and the electronic properties have been investigated by Current-Voltage (I-V), Capacitance-Voltage (C-V) and Deep level transient spectroscopy (DLTS) measurements. DLTS measurements show two dominants electron traps at the interface of the ZnO/n-Si junction with energy position at 0.07 eV and 0.15 eV below the conduction band edge, labelled E(0.07) and E(0.15), respectively, and no electrically active defects at the interface of the ZnO/p-Si junction. E(0.07) is reduced by annealing up to 400°C while E(0.15) is created at 500°C. The best heterostructure is found after heat treatment at 400°C with a substantial improvement of the current rectification for ZnO/n-Si and the formation of Ohmic contact on ZnO/p-Si. A reduction of the interface defects correlates with an improvement of the crystal structure of the ZnO film with a preferred orientation along the c-axis.

Electronic properties of the ZnO:Al/n-Si (100), (110) and (111) interfaces

2014 ◽  
Vol 1699 ◽  
Author(s):  
Per Lindberg ◽  
Vincent Quemener ◽  
Kristin Bergum ◽  
Jiantuo Gan ◽  
Bengt G. Svensson ◽  
...  
Keyword(s):  
Deep Level ◽  
Atomic Layer ◽  
Fused Silica ◽  
X Ray Diffraction ◽  
X Ray ◽  
Si Substrates ◽  
Layer Deposition ◽  
Current Voltage ◽  
Transient Spectroscopy ◽  
Post Deposition

ABSTRACTAluminum doped ZnO (AZO) has been deposited on (100), (110) and (111) oriented n-type Si and on fused silica by atomic layer deposition (ALD). The films have been post deposition annealed in the temperature range 200-500 οC. The AZO films have been characterized by X-ray diffraction (XRD), Hall and transmittance measurements. Circular diodes have been fabricated from the AZO/Si structures and characterized by current-voltage (IV) and deep level transient spectroscopy (DLTS). The AZO films form Schottky junctions with the Si substrates for all the crystallographic orientations. It is established that after post deposition annealing the structure AZO/n-Si (110) is distinguished as the system with largest rectification.

Effect of Thermal Annealing on La2O3 Films Grown by Plasma Enhanced Atomic Layer Deposition

2015 ◽  
Vol 1088 ◽  
pp. 107-111
Author(s):  
Jian Shuang Liu ◽  
Fang Fang Zhu ◽  
Fei Lu ◽  
Lin Zhang
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Deposition Process ◽  
Flat Band ◽  
Interface Reactions ◽  
Layer Deposition ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Before And After ◽  
Current Voltage Characteristics

A plasma enhanced atomic layer deposition process has been demonstrated for Lanthanum oxide films using La (thd)3 precursor and oxygen plasma. The chemical and electrical properties of La2O3 ultra-thin films on Si (100) substrates before and after post-annealing in N2 ambient have been investigated. X-ray photoelectron spectroscopic revealed that interface reactions take place after annealing process which lead to oxygen insufficiency, as well as the balance band offset decreases with the increase of annealing temperature. The capacitance-voltage and current-voltage characteristics show La2O3 capacitors annealed at 900 °C have negligible hysteresis, smaller interface trap density in comparison with as-deposited samples, but larger flat band voltage and higher gate-leakage current density due to the appearance of oxygen vacancy in the La2O3 films.

scholarly journals Electronic Properties and Density of States of Self-Assembled GaSb/GaAs Quantum Dots

2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
T. Nowozin ◽  
A. Wiengarten ◽  
L. Bonato ◽  
D. Bimberg ◽  
Wei-Hsun Lin ◽  
...  
Keyword(s):  
Electronic Properties ◽  
Density Of States ◽  
Deep Level ◽  
Material System ◽  
A Value ◽  
Capacitance Voltage ◽  
Different Temperatures ◽  
Self Assembled ◽  
Transient Spectroscopy ◽  
The Individual

The electronic properties of a self-assembled GaSb/GaAs QD ensemble are determined by capacitance-voltage (C-V) and deep-level transient spectroscopy (DLTS). The charging and discharging bias regions of the QDs are determined for different temperatures. With a value of 335 (±15) meV the localization energy is rather small compared to values previously determined for the same material system. Similarly, a very small apparent capture cross section is measured (1·10−16 cm2). DLTS signal analysis yields an equivalent to the ensemble density of states for the individual energies as well as the density function of the confinement energies of the QDs in the ensemble.

Electronic Properties Of Defects Formed In n-Si During Sputter-Etching In An Ar Plasma

1996 ◽  
Vol 442 ◽  
Author(s):  
P. N. K. Deenapanray ◽  
F. D. Auret ◽  
C. Schutte ◽  
G. Myburg ◽  
W. E. Meyer ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Deep Level ◽  
High Energy ◽  
Barrier Heights ◽  
Opposite Trend ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Ar Plasma ◽  
Transient Spectroscopy ◽  
Sputter Etching

AbstractWe have employed current-voltage (IV), capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) techniques to characterise the defects induced in n-Si during RF sputter-etching in an Ar plasma. The reverse leakage current, at a bias of 1 V, of the Schottky barrier diodes fabricated on the etched samples was found to decrease with etch time reaching a minimum at 6 minutes and thereafter increased. The barrier heights followed the opposite trend. The plasma processing introduced six prominent deep levels below the conduction band of the substrate. A comparison with the defects induced during high energy (MeV) alpha-particle, proton and electron irradiation of the same material revealed that plasma-etching created the VO- and VP-centres, and V2-10. Some of the remaining sputter-etching-induced (SEI) defects have tentatively been related to those formed during either 1 keV He- or Ar-ion bombardment.

Laplace Transform Deep Level Transient Spectroscopy Study of the EH6/7 Center

2013 ◽  
Vol 740-742 ◽  
pp. 645-648 ◽  
Author(s):  
Giovanni Alfieri ◽  
Tsunenobu Kimoto
Keyword(s):  
Laplace Transform ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Dose Dependence ◽  
Conduction Band Edge ◽  
Emission Rates ◽  
Energy Position ◽  
Low Energy Electron ◽  
Transient Spectroscopy ◽  
Electric Filed

We employed Laplace transform deep level transient spectroscopy (LDLTS) for the resolution of the EH6/7 center in n-type 4H-SiC epilayers. Our results suggest that this technique is effective in separating the emission rates of the EH6 and EH7 levels. From the Arrhenius dependence of the emission rates we could estimate the energy position of EH6 and EH7 as 1.39 and 1.49 eV below the minimum of the conduction band edge, respectively. Generation of of EH6 and EH7 centers by low-energy electron irradiation (dose dependence) was also investigated. At last, a double pulse Laplace DLTS is performed in order to show the electric filed dependence of the emission rates of EH6 and EH7.

Characterization of CdS–CuInSe2 solar cells by current–voltage, capacitance–voltage, and capacitance-transient measurements

1987 ◽  
Vol 65 (8) ◽  
pp. 966-971 ◽  
Author(s):  
N. Christoforou ◽  
J. D. Leslie ◽  
S. Damaskinos
Keyword(s):  
Solar Cells ◽  
Deep Level ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Carrier Trap ◽  
Transient Spectroscopy ◽  
Increasing Temperature ◽  
P Type ◽  
Capacitance Transient ◽  
Transient Measurements

CdS–CuInSe2 solar cells, which have an efficiency of 9%, have been studied by current–voltage, capacitance–voltage, and capacitance-transient measurements over the temperature range 90–380 K. Deep-level transient spectroscopy analysis of the capacitance transient measurements reveals one majority carrier trap with an activation energy of 0.70 ± 0.02 eV. Although the present experiment cannot establish definitely if the trap is in the CdS or CuInSe2 layer, arguments are presented that it is a hole trap in the p-type CuInSe2 layer. Current–voltage measurements indicate a reversible increase in the reverse-bias leakage current with increasing temperature above 300 K. Evidence is presented that suggests that the rectifying barrier height in the CdS–CuInSe2 solar cell decreases rapidly with temperature above 300 K. Capacitance versus voltage measurements suggest that the depiction layer being studied is primarily in the CuInSe2, but the temperature dependence of the ionized charge concentration N(x) cannot be totally explained although one possible cause is suggested.

DLTS Studies of Al Diffused n-Si

2010 ◽  
Vol 442 ◽  
pp. 393-397
Author(s):  
S. Siddique ◽  
M.M. Asim ◽  
F. Saleemi ◽  
S. Naseem
Keyword(s):  
Cross Section ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Dlts Spectrum ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Junction Formation ◽  
Transient Spectroscopy ◽  
Phosphorus Doped ◽  
Si Wafer

We have studied the electrical properties of Si p-n junction diodes by deep level transient spectroscopy (DLTS) measurements. The p-n junctions were developed on a Phosphorus doped Si by depositing Al and annealing at various temperatures. In order to confirm junction formation, current-voltage and capacitance-voltage measurements were made. Two deep levels at Ec-0.17 eV (E1) and Ec-0.44 eV (E2) were observed in the DLTS spectrum. These traps have been characterized by their capture cross-section, activation energy level and trap density. On the basis of these parameters, level E1 can be assigned as V-O complex and E2 as P-V complex. These traps are related to the growth of n-Si wafer and not due to Al diffusion.

scholarly journals Evolution of Electronic Properties of Cu(In, Ga)Se2 (CIGS)-Based Solar Cells During a 3-stage Growth Process

2003 ◽  
Vol 763 ◽  
Author(s):  
Jehad A. AbuShama ◽  
S. Johnston ◽  
R. Ahrenkiel ◽  
R. Crandall ◽  
D. Young ◽  
...  
Keyword(s):  
Solar Cells ◽  
Electronic Properties ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Thin Film Solar Cells ◽  
Polycrystalline Thin Film ◽  
Capacitance Voltage ◽  
Carrier Traps ◽  
Stage Process ◽  
Transient Spectroscopy

AbstractWe investigated the electronic properties of ZnO/CdS/CIGS/Mo/SLG polycrystalline thin-film solar cells with compositions ranging from Cu-rich to In(Ga)-rich by deep-level transient spectroscopy (DLTS) and capacitance-voltage (C-V) measurements. This compositional change represents the evolution of the film during growth by the 3-stage process. Two sets (four samples each) of CIGS thin films were prepared with Ga/(In+Ga) ratios of ∼0.3 (low Ga) and ∼0.6 (high Ga). The Cu/(In+Ga) ratio ranges from 1.24 (Cu-rich) to 0.88 (In(Ga)-rich). The films were treated with NaCN to remove the Cu2-xSe phase where needed. Key results include: (1) For lowGa devices, DLTS data show that acceptor-like traps dominate in samples where CIGS grains do not go through the Cu-rich to In(Ga)-rich transition, whereas donor-like traps dominate in In(Ga)-rich samples. Therefore, we see a clear transformation of defects from acceptor-like to donor-like traps. The activation energies of these traps range from 0.12 to 0.63 eV. We also observed that NaCN treatment eliminates a deep minority trap in the In(Ga)-rich devices, (2) For high-Ga devices, only majority-carrier traps were detected. These traps again range from shallow to deep, (3) The carrier concentration around the junction and the density of traps decrease as the CIGS becomes more In(Ga)-rich.

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