Electronic Properties Of Defects Formed In n-Si During Sputter-Etching In An Ar Plasma

1996 ◽  
Vol 442 ◽  
Author(s):  
P. N. K. Deenapanray ◽  
F. D. Auret ◽  
C. Schutte ◽  
G. Myburg ◽  
W. E. Meyer ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Deep Level ◽  
High Energy ◽  
Barrier Heights ◽  
Opposite Trend ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Ar Plasma ◽  
Transient Spectroscopy ◽  
Sputter Etching

AbstractWe have employed current-voltage (IV), capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) techniques to characterise the defects induced in n-Si during RF sputter-etching in an Ar plasma. The reverse leakage current, at a bias of 1 V, of the Schottky barrier diodes fabricated on the etched samples was found to decrease with etch time reaching a minimum at 6 minutes and thereafter increased. The barrier heights followed the opposite trend. The plasma processing introduced six prominent deep levels below the conduction band of the substrate. A comparison with the defects induced during high energy (MeV) alpha-particle, proton and electron irradiation of the same material revealed that plasma-etching created the VO- and VP-centres, and V2-10. Some of the remaining sputter-etching-induced (SEI) defects have tentatively been related to those formed during either 1 keV He- or Ar-ion bombardment.

Electronic Properties of ZnO/Si Heterojunction Prepared by ALD.

2011 ◽  
Vol 178-179 ◽  
pp. 130-135 ◽  
Author(s):  
Vincent Quemener ◽  
Mari Alnes ◽  
Lasse Vines ◽  
Ola Nilsen ◽  
Helmer Fjellvåg ◽  
...  
Keyword(s):  
Electronic Properties ◽  
Deep Level ◽  
Atomic Layer ◽  
Substantial Improvement ◽  
Conduction Band Edge ◽  
Energy Position ◽  
Layer Deposition ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

ZnO/n-Si and ZnO/p-Si heterostructures were prepared by Atomic layer deposition (ALD) and the electronic properties have been investigated by Current-Voltage (I-V), Capacitance-Voltage (C-V) and Deep level transient spectroscopy (DLTS) measurements. DLTS measurements show two dominants electron traps at the interface of the ZnO/n-Si junction with energy position at 0.07 eV and 0.15 eV below the conduction band edge, labelled E(0.07) and E(0.15), respectively, and no electrically active defects at the interface of the ZnO/p-Si junction. E(0.07) is reduced by annealing up to 400°C while E(0.15) is created at 500°C. The best heterostructure is found after heat treatment at 400°C with a substantial improvement of the current rectification for ZnO/n-Si and the formation of Ohmic contact on ZnO/p-Si. A reduction of the interface defects correlates with an improvement of the crystal structure of the ZnO film with a preferred orientation along the c-axis.

Characterization of CdS–CuInSe2 solar cells by current–voltage, capacitance–voltage, and capacitance-transient measurements

1987 ◽  
Vol 65 (8) ◽  
pp. 966-971 ◽  
Author(s):  
N. Christoforou ◽  
J. D. Leslie ◽  
S. Damaskinos
Keyword(s):  
Solar Cells ◽  
Deep Level ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Carrier Trap ◽  
Transient Spectroscopy ◽  
Increasing Temperature ◽  
P Type ◽  
Capacitance Transient ◽  
Transient Measurements

CdS–CuInSe2 solar cells, which have an efficiency of 9%, have been studied by current–voltage, capacitance–voltage, and capacitance-transient measurements over the temperature range 90–380 K. Deep-level transient spectroscopy analysis of the capacitance transient measurements reveals one majority carrier trap with an activation energy of 0.70 ± 0.02 eV. Although the present experiment cannot establish definitely if the trap is in the CdS or CuInSe2 layer, arguments are presented that it is a hole trap in the p-type CuInSe2 layer. Current–voltage measurements indicate a reversible increase in the reverse-bias leakage current with increasing temperature above 300 K. Evidence is presented that suggests that the rectifying barrier height in the CdS–CuInSe2 solar cell decreases rapidly with temperature above 300 K. Capacitance versus voltage measurements suggest that the depiction layer being studied is primarily in the CuInSe2, but the temperature dependence of the ionized charge concentration N(x) cannot be totally explained although one possible cause is suggested.

DLTS Studies of Al Diffused n-Si

2010 ◽  
Vol 442 ◽  
pp. 393-397
Author(s):  
S. Siddique ◽  
M.M. Asim ◽  
F. Saleemi ◽  
S. Naseem
Keyword(s):  
Cross Section ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Dlts Spectrum ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Junction Formation ◽  
Transient Spectroscopy ◽  
Phosphorus Doped ◽  
Si Wafer

We have studied the electrical properties of Si p-n junction diodes by deep level transient spectroscopy (DLTS) measurements. The p-n junctions were developed on a Phosphorus doped Si by depositing Al and annealing at various temperatures. In order to confirm junction formation, current-voltage and capacitance-voltage measurements were made. Two deep levels at Ec-0.17 eV (E1) and Ec-0.44 eV (E2) were observed in the DLTS spectrum. These traps have been characterized by their capture cross-section, activation energy level and trap density. On the basis of these parameters, level E1 can be assigned as V-O complex and E2 as P-V complex. These traps are related to the growth of n-Si wafer and not due to Al diffusion.

Evidence of Defect Migration and Clustering in MeV Heavy Ion Damaged Silicon

1998 ◽  
Vol 510 ◽  
Author(s):  
Y.N. Mohapatra ◽  
P.K. Girl
Keyword(s):  
Room Temperature ◽  
Deep Level ◽  
Heavy Ion ◽  
High Dose ◽  
Defect Migration ◽  
Defect Profile ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy ◽  
Limited Conduction

AbstractWe have studied electrically active defects created by MeV heavy ion implantation in n-silicon. The buried damaged layer, created by implanting Ar’ ions of energy 1.45 MeV and doses in the range 1013-1014 cm−2 at room temperature, is embedded within the depletion layer of a Schottky diode. The defects are characterized using capacitance-voltage (C-V), current-voltage (I-V) and deep level transient spectroscopy (DLTS). Large concentration of electrically active defects are found to occur in a region several microns beyond the ion range or the damage profile predicted by Monte Carlo simulations. The dominance of a single trap in the damaged region is established from hysteresis effect in C-V, space charge limited conduction in forward I-V characteristics and DLTS results. With annealing in the temperature range of 400-600C, the observed changes in defect charge profile indicate that the effective electrical interface moves progressively towards the surface. C-V characteristics have been simulated using model charge profiles which suggest presence of a compensated region and a sharp negatively charged defect profile at a distance much larger than that expected from ion range. Our results constitute experimental evidence of migration and clustering of interstitial related defects, even at room temperature in case of high dose irradiation.

Electronic Levels Induced by Irradiation in 4H-Silicon Carbide

2005 ◽  
Vol 483-485 ◽  
pp. 359-364 ◽  
Author(s):  
Antonio Castaldini ◽  
Anna Cavallini ◽  
L. Rigutti ◽  
Filippo Nava
Keyword(s):  
Silicon Carbide ◽  
Deep Level ◽  
Particle Energy ◽  
Free Carrier ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Current Voltage Characteristics ◽  
Transient Spectroscopy ◽  
Induced Defects ◽  
Irradiation Induced Defects

The effects of irradiation with protons and electrons on 4H-silicon carbide epilayers were investigated. The particle energy was 6.5 and 8.2 MeV. The electronic levels associated with the irradiation-induced defects were analyzed by current-voltage characteristics and deep level transient spectroscopy measurements up to 700 K. In the same temperature range the apparent free carrier concentration was measured by capacitance-voltage characteristics to monitor possible compensation effects due to the deep level associated to the induced defects. Introduction rate, enthalpy and capture cross-section of such deep levels were compared and some conclusions about the nature of the defects were drawn.

Defects in High Energy Ion Irradiated 4H-SiC

2009 ◽  
Vol 615-617 ◽  
pp. 397-400 ◽  
Author(s):  
Gaetano Izzo ◽  
Grazia Litrico ◽  
Andrea Severino ◽  
Gaetano Foti ◽  
Francesco La Via ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deep Level Transient Spectroscopy ◽  
Ion Irradiation ◽  
Deep Level ◽  
High Energy ◽  
Conduction Band Edge ◽  
Transmission Electron ◽  
Current Voltage ◽  
Transient Spectroscopy ◽  
Fluence Range

The defects produced by 7.0 MeV C+ irradiation in 4H-SiC epitaxial layer were followed by Deep Level Transient Spectroscopy, current-voltage measurements and Transmission Electron Microscopy in a large fluence range (109-51013 ions/cm2). At low fluence (109 -1010 ions/cm2), the formation of three main level defects located at 0.68 eV, 0.98 eV and 1.4 eV below the conduction band edge is detected. The trap concentration increases with ion fluence suggesting that these levels are associated to the point defects generated by ion irradiation. In this fluence range the leakage current of the diodes does not change. At higher fluence an evolution of defects occurs, as the concentration of traps at 0.68 eV and 1.4 eV decreases, while the intensity of the level at 0.98 eV remains constant. In this fluence range complex defects are formed and an increase of a factor five in the leakage current is measured.

scholarly journals Слои кремния, гиперпересыщенные теллуром, для фотодиодов видимого и инфракрасного диапазонов

2021 ◽  
Vol 91 (12) ◽  
pp. 2026
Author(s):  
Ф.Ф. Комаров ◽  
C.Б. Ластовский ◽  
И.А. Романов ◽  
И.Н. Пархоменко ◽  
Л.А. Власукова ◽  
...  
Keyword(s):  
Laser Annealing ◽  
Deep Level ◽  
Structural Defects ◽  
Pulsed Laser Annealing ◽  
Near Ir ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy ◽  
Spectral Ranges ◽  
Hyperdoped Silicon

Silicon layers doped with tellurium up to concentration (3–5)·1020 cm-3 have been formed by ion implantation with subsequent pulsed laser annealing. It was shown that 70–90% of the introduced impurity is in the substitution position in the silicon lattice. Si layers Tellurium- hyperdoped silicon layers exhibit significant absorption (35–65%) both in the visible and near IR (1100–2500 nm) spectral ranges, and the absorption increases with increasing wavelength. The current-voltage and capacitance-voltage characteristics, as well as the photosensitivity of photodetectors based on Te-doped silicon layers have been presented and discussed. The residual structural defects in implanted Si layers have been considered by deep-level transient spectroscopy.

scholarly journals Current--Voltage, Capacitance--Voltage--Temperature, and DLTS Studies of Ni|6H-SiC Schottky Diode

2021 ◽  
Vol 55 (4) ◽  
pp. 388
Author(s):  
A. Rabehi ◽  
B. Akkal ◽  
M. Amrani ◽  
S. Tizi ◽  
Z. Benamara ◽  
...  
Keyword(s):  
Barrier Height ◽  
Schottky Diode ◽  
Ideality Factor ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Schottky Diodes ◽  
Double Barrier ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

In this paper, we give a systematical description of Ni|6H-SiC Schottky diode by current--voltage I(V) characteristics at room temperature and capacitance--voltage C(V) characteristics at various frequencies (10-800 kHz) and various temperatures (77-350oK). The I(V) characteristics show a double-barrier phenomenon, which gives a low and high barrier height (phiLbn=0.91 eV, phiHbn=1.55 eV), with a difference of Deltaphibn=0.64 eV. Also, low ideality factor nL=1.94 and high ideality factor nH=1.22 are obtained. The C-V-T measurements show that the barrier height phibn decreases with decreasing of temperature and gives a temperature coefficient alpha=1.0·10-3 eV/K and phibn(T=0 K)=1.32 eV. Deep-level transient spectroscopy (DLTS) has been used to investigate deep levels in the Ni|6H-SiC Schottky diode. The traps signatures such as activation energies Ea=0.50±0.07 eV, capture cross-section sigma=1.8·10-20 cm2, and defect concentration NT=6.2·1013 cm-3 were calculated from Arrhenius plots. Keywords: si1licon carbide, Schottky diodes, I-V, C-V-T, deep-level transient spectroscopy (DLTS).

Trapping Behavior of Thin Siliconoxynitride Layers Prepared by Rapid Thermal Processing

1996 ◽  
Vol 428 ◽  
Author(s):  
R. Beyer ◽  
H. Burghardt ◽  
R. Reich ◽  
E. Thomas ◽  
D. Grambole ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Interface State ◽  
Oxidation States ◽  
Nuclear Reaction Analysis ◽  
Depth Profiles ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

AbstractSiliconoxynitride layers with thicknesses between 5 and 10 nm were grown on (100) oriented silicon by rapid thermal processing (RTP) using either N2O or NH3 as nitridant. In order to study the trapping behaviour at the interface and in the insulator bulk, capacitance-voltage (CV) and current-voltage (IV) measurements have been performed combined with different magnitudes of Fowler-Nordheim stress. In addition, Deep Level Transient Spectroscopy (DLTS) has been applied for interface state detection. Auger Electron Spectroscopy (AES) has been used to obtain depth profiles for Si, N, O and C. The deconvolution of the AES signal displays significant peak contributions related to intermedium oxidation states. Nuclear Reaction Analysis (NRA) was successfully applied for hydrogen detection in buried SiOxNy thin films.

Sign in / Sign up

Export Citation Format

Share Document