Comparison of Gate Oxide Processing Techniques for Thin Dielectric Films

1996 ◽  
Vol 446 ◽  
Author(s):  
Pat Schay ◽  
Fuyu Lin ◽  
Sergio Ajuria ◽  
John Stih
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Electrical Performance ◽  
Dielectric Films ◽  
Total Thickness ◽  
Large Area ◽  
Processing Techniques ◽  
Thin Dielectric Films

AbstractThis paper focuses on establishing a baseline for thin dielectric processes including: low temperature, dilute, stacked (TEOS), oxynitride, and high temperature annealed (grow‐anneal‐grow) oxidation. 105Å (total thickness) gate dielectrics were grown or deposited for this study. The stack oxide showed the highest Vbd yields for both large‐area and edge‐intensive capacitors, but the poorest Qbd. The N2O oxide yielded mediocre Vbd and Qbd. The low temperature and dilute oxides showed early breakdowns, but acceptable Qbd. 900°C thermal gate oxide showed slightly better average Vbd than low temperature and dilute oxides but comparable Qbd. The high temperature annealed oxide appears to have the best electrical performance, but the worst uniformity.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

The Electrical Phenomena of Non-planar Structure and Devices using Plasma Doping

2005 ◽  
Vol 864 ◽  
Author(s):  
Jong-Heon Yang ◽  
In-Bok Baek ◽  
Kiju Im ◽  
Chang-Geun Ahn ◽  
Sungkweon Baek ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Thermal Annealing ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Oxide Interface ◽  
Substrate Heating ◽  
Plasma Doping ◽  
Device Reliability ◽  
Research Show

AbstractWe fabricated narrow fins structures and non-planar MOSFETs like FinFETs and triple-gate MOSFETs using plasma doping with substrate heating under 350··, and measured their I-V characteristics. Fins and MOSFETs using low-temperature doping process show good current drivability and low subthreshold slope. However, without post high-temperature thermal annealing, this process could not avoid generating defects and traps as well as mobile protons on the gate and gate oxide interface and junctions, and therefore degraded device reliability. The results of ultra-small MOSFET research show possibility of new memory devices with these traps and ions in devices.

Controlled Thin Oxidation and Nitridation in a Single Wafer Cluster Tool

1995 ◽  
Vol 387 ◽  
Author(s):  
I. Sagnes ◽  
D Laviale ◽  
F. Glowacki ◽  
B. Blanchard ◽  
F. Martin
Keyword(s):  
Surface Preparation ◽  
Gate Oxide ◽  
Dielectric Films ◽  
Gate Oxides ◽  
Thermal Budget ◽  
Precise Control ◽  
Boron Penetration ◽  
Gate Resistance ◽  
Thin Dielectric Films ◽  
Cluster Tool

abstractFor both advanced MOS technologies (gate length ≤ 0.25.μm) and EEPROMs, the quality and reproducibility of thin dielectric films (≤ 6 nm) are essential. To obtain such dielectrics involves very precise control of the silicon surface preparation and gate oxide growth. Furthermore, research into such supplementary properties of oxide as improved SiO2/Si interface resistance to current injections or enhanced p+gate resistance to boron penetration in the channel may require nitridation treatment. Such a sequence of steps can be carried out under controled atmosphere using a cluster tool. This paper presents the preliminary results obtained in a single wafer cluster tool on i) the surface preparation under ozone of a silicon wafer immediately after diluted liquid HF treatment and ii) the nitridation of the 6 nm gate oxide under low temperature, low pressure gaseous NO. It is shown that the NO molecule can be successfully used in Rapid Thermal Processing (RTP) and allows gate oxides to be nitrided with properties at least equivalent to those obtained under N2O nitridation, but with a strikingly reduced thermal budget.

Characterization of Large Area 4H-SiC and 6H-SiC Capacitive Devices at 600 °C

2012 ◽  
Vol 717-720 ◽  
pp. 1187-1189
Author(s):  
Ruby N. Ghosh ◽  
Reza Loloee
Keyword(s):  
High Temperature ◽  
Field Effect ◽  
Gate Oxide ◽  
Voltage Characteristic ◽  
Capacitive Sensors ◽  
Large Area ◽  
Signal Noise ◽  
Capacitance Voltage ◽  
Corrosive Environments

SiC based capacitive devices have the potential to operate in high temperature, chemically corrosive environments provided that the electrical integrity of the gate oxide and metallization can be maintained in these environments. We report on the performance of large area, up to 8 x 10-3 cm2, field-effect capacitive sensors fabricated on both the 4H and 6H polytypes at 600°C. Large area capacitors improve the signal/noise (S/N) ratio which is proportional to the slope of the capacitance-voltage characteristic. At 600 °C we obtain a S/N ~ 20. The device response is independent of polytype, either 4H or 6H-SiC. These results demonstrate the reliability of our field-effect structure, operating as a simple potentiometer at high temperature.

Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

2000 ◽  
Vol 654 ◽  
Author(s):  
X. Duan ◽  
K. Kisslinger ◽  
L. Mayes ◽  
S. Ruby ◽  
J. Barrett
Keyword(s):  
Electron Microscopy ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Atomic Level ◽  
Electrical Performance ◽  
Interface Morphology ◽  
Gate Oxides ◽  
Mos Devices ◽  
Transmission Electron ◽  
The Impact

AbstractThe Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

The Application of Laser Annealing to the Fabrication of Impatt Diode Structures

1984 ◽  
Vol 35 ◽  
Author(s):  
Anthony E Adams ◽  
L A Hing
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Epitaxial Growth ◽  
Laser Processing ◽  
Laser Annealing ◽  
Boron Diffusion ◽  
Impatt Diode ◽  
Processing Techniques ◽  
P Type ◽  
Temperature Time

ABSTRACTThe conventional method for fabricating silicon IMPATT diode structures involves the epitaxial growth of successive n- and p-type layers onto a n+ substrate followed by a boron diffusion to form the final p+ layer. The high temperature time cycles experienced by the structure during these processes cause junction interfaces to become degraded through dopant diffusion. In this paper we examine the application of laser processing techniques to the epitaxial regrowth of low temperature deposited layers and report on the nature of the recrystallised material.

The Effect of Impurities in Tin Film When Used As Mos Gate Electrodes

1998 ◽  
Vol 514 ◽  
Author(s):  
H. Yag ◽  
J. C. Hu ◽  
J. P. Lu ◽  
G. A. Brown ◽  
A. L. P. Rotondara ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Oxide ◽  
Electrical Performance ◽  
Process Conditions ◽  
High Temperature Stability ◽  
Tin Films ◽  
Gate Electrodes ◽  
Tin Film ◽  
Thin Gate Oxide ◽  
Mos Gate

ABSTRACTRefractory metal gates have been studied for CMOS gate electrodes on ultra thin gate oxide due to its midgap work function, low resistivity and no gate depletion, etc. In particular, titanium nitride received most attention because of its process maturity and its good diffusion barrier properties for backend applications. Different TiN film properties are important when TiN is used as a gate material than when it is used for backend applications. One issue is the effect of TiN film impurities on the gate oxides and their high temperature stability since some high temperature processes are usually needed after gate formation. This paper reports the study of different TiN films used as MOS gate electrodes on ultra thin gate oxide and the effects of their impurities on gate oxide electrical performance. PVD TiN films deposited with different process conditions show different oxygen content, and different gate oxide properties were observed when these PVD TiN films were used as gate electrodes. On the other hand CVD TiN films deposited using different precursors also showed different impurities, including carbon, oxygen or silicon, which largely affect CVD TiN performance when used as gate material. The different TiN films were characterized by X-ray glancing angle reflection, XPS, SIMS and TEM, and the electrical properties were studied by I-V, C-V, charge to breakdown (Qbd) and ramp voltage breakdown tests on MOS capacitors. The results showed that the high purity TiN films provide stable gate material with small damage to the gate oxide, but impurities, especially oxygen, affect the gate oxide properties after high temperature anneal. However, due to the different TiN process capabilities, TiN films with impurities may still have advantages over pure TiN film in some cases of different MOS gate applications.

Electrical Properties of Oxide-Nitride-Oxide, Ono, Heterostructures Fabricated by Low Temperature Remote PECVD

1992 ◽  
Vol 284 ◽  
Author(s):  
Y. Ma ◽  
T. Yasuda ◽  
Y. L. Chen ◽  
G. Lucovsky ◽  
D. M. Maher
Keyword(s):  
High Temperature ◽  
Electrical Properties ◽  
Low Temperature ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Flat Band ◽  
Metal Insulator ◽  
Thermally Grown Oxides ◽  
Dielectric Interfaces ◽  
Nitride Oxide

ABSTRACTOxide-Nitride-Oxide, ONO, heterostructures, fabricated by low-temperature, 300°C, Remote Plasma Enhanced Chemical Vapor Deposition, have been used as gate dielectrics in metal insulator semiconductor devices. Analysis of C-V data for this devices indicates that higher levels of fixed charge are associated with the internal dielectric interfaces. A high-temperature, ̃900°C, Rapid Thermal Annealing, RTA, step has been inserted into the process sequence for fabricating ultra-thin, 4.7 nm SiO2 equivalent, device-quality ONO dielectric layers. The electrical properties of these ONO dielectrics, including the Si/SiO2 interfacial trap density, the flat band voltage, the charge to breakdown and the reliability under electron injection are comparable to those of high temperature, thermally-grown oxides.

Sign in / Sign up

Export Citation Format

Share Document