Hot Carrier Reliability in Sub-0.1 μm nMOSFET Devices

1996 ◽  
Vol 428 ◽  
Author(s):  
Samar K. Saha
Keyword(s):  
Impact Ionization ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Ionization Rate ◽  
Systematic Investigation ◽  
Short Channel ◽  
Carrier Heating ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Channel Lengths

AbstractThis paper presents a systematic investigation of the hot-carrier effect in deep sub-micron silicon nMOSFET devices. A Hydrodynamic model for semiconductors was used to simulate the local carrier heating and the non-local transport phenomena in nMOSFETs of effective channel lengths 41, 66, 96, and 126 nrn under various biasing conditions. Test structures for device simulation were generated by using a super-steep retrograde channel profile with subsurface peak concentration of l×1018 cm−3, and a gate oxide thickness of 3 nm. Superb MOSFET device characteristics were obtained for all devices. The simulation results show a significant decrease in substrate current, electron impact ionization rate, and peak electron temperature near the drain end of the channel with the decrease in supply voltage. The distribution of electrons into the substrate due to local electron heating is shown to be responsible for hot-carrier reliability in ultra-short channel silicon nMOSFET devices.

Effect of Channel Profile Engineering on Hot Carrier Reliability in nMOSFETs with 100 nm Channel Lengths

1997 ◽  
Vol 473 ◽  
Author(s):  
Samar K. Saha
Keyword(s):  
Supply Voltage ◽  
High Surface ◽  
Device Simulation ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Hot Carrier ◽  
Hot Carrier Effects ◽  
Doping Profiles ◽  
Substrate Concentrations

ABSTRACTHot-carrier effect was studied for different channel doping profiles in nMOSFET devices with effective channel length near 100 nm using a device simulator. The test structures for device simulation were generated using gate oxide thickness of 3 nm. The channel doping profiles used were abrupt- and graded-retrograde types with low surface and high substrate concentrations, and conventional step profiles with high surface and low substrate concentrations. For accurate device simulation, a hydrodynamic model for semiconductors was used to simulate the non-local transport phenomena in the devices. The simulation results indicate that for ultra-short channel devices, the current drivability and the hot-carrier effects depend on the shape of channel doping profiles. For a given supply voltage, the hot-carrier effects in ultra-short channel devices can be controlled by optimizing the channel doping profiles.

Hot-Carrier Effect in Submicron pMOSFETs

1995 ◽  
Vol 391 ◽  
Author(s):  
S. Saha ◽  
C. S. Yeh ◽  
Ph. Lindorfer ◽  
J. Luo ◽  
U. Nellore ◽  
...  
Keyword(s):  
Impact Ionization ◽  
Ionization Rate ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Substrate Current ◽  
Lateral Channel ◽  
Ionization Model ◽  
Hot Carrier Effect ◽  
Impact Ionization Rate ◽  
The Impact

AbstractThis paper describes an application of process and device simulation programs in the study of substrate current generated by hot-carrier effect in submicron p-channel MOSFET devices. The impact ionization model for holes was calibrated for accurate simulation of substrate current in submicron devices, and an expression for the impact ionization rate of holes in silicon is obtained. The simulated substrate current for 0.57, 0.73 and 1.13 μm devices obtained by the optimized expression agrees very well with the measured data. The optimized impact ionization expression was also used to simulate the effect of p- Lightly Doped Drain impurity profile on substrate current, and the simulated peak substrate current and the corresponding maximum lateral channel electric field as a function of p- dose and length are presented.

Hot Carrier Effects in Deep Submicron Nmosfets

1996 ◽  
Vol 428 ◽  
Author(s):  
Abhijit Phanse ◽  
Samar Saha
Keyword(s):  
Electric Fields ◽  
Channel Length ◽  
Deep Submicron ◽  
Short Channel ◽  
Hot Carrier ◽  
Velocity Saturation ◽  
Substrate Current ◽  
Hot Carrier Effects ◽  
Saturation Effects ◽  
Channel Lengths

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

Hot-Carrier Effect on TID Irradiated Short-Channel UTTB FD-SOI n-MOSFETs

2018 ◽  
Author(s):  
Jiangwei Cui ◽  
Qiwen Zheng ◽  
Bingxu Ning ◽  
Xuefeng Yu ◽  
Kai Zhao ◽  
...  
Keyword(s):  
Short Channel ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Hot Carrier Effect

Short-Channel Effects in 4H-SiC MOSFETs

2005 ◽  
Vol 483-485 ◽  
pp. 821-824
Author(s):  
Masato Noborio ◽  
Y. Kanzaki ◽  
Jun Suda ◽  
Tsunenobu Kimoto ◽  
Hiroyuki Matsunami
Keyword(s):  
Threshold Voltage ◽  
Empirical Relationship ◽  
Device Simulation ◽  
Oxide Thickness ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Channel Lengths ◽  
P Type

Short-channel effects in SiC MOSFETs have been investigated. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (000-1) and (11-20) faces.^Short-channel effects such as punchthrough behavior, decrease of threshold voltage and deterioration of subthreshold characteristics are observed. Furthermore, the critical channel lengths below which short-channel effects occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths in the fabricated SiC MOSFETs are in agreement with those obtained from the device simulation. The results are also in agreement with the empirical relationship for Si MOSFETs.

Channel Hot-Carrier Effect of 4H-SiC MOSFET

2009 ◽  
Vol 615-617 ◽  
pp. 813-816 ◽  
Author(s):  
Liang Chun Yu ◽  
Kin P. Cheung ◽  
John S. Suehle ◽  
Jason P. Campbell ◽  
Kuang Sheng ◽  
...  
Keyword(s):  
Impact Ionization ◽  
Power Device ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Hot Carrier Effect ◽  
High Level ◽  
First Time ◽  
Hot Carrier Degradation

SiC MOSFET, as power device, can be expected to operate with high drain and high gate voltages, possibly leading to hot-carrier effect. However, hot-carrier degradation in a SiC MOSFET is difficult to detect because the as fabricated devices contain high level of defects. We report, for the first time, evidence of hot-carrier effect in 4H-SiC MOSFET. The result suggests that hot hole from impact ionization trapped in the oxide is the cause of the channel hot-carrier effect.

scholarly journals Impact of Split Gate in a Novel SOI MOSFET (SPG SOI) for Reduction of Short-Channel Effects: Analytical Modeling and Simulation

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Mohammad K. Anvarifard ◽  
Ali A. Orouji
Keyword(s):  
Step Function ◽  
Simulation Software ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Hot Carrier ◽  
Novel Device ◽  
Carrier Effect ◽  
Channel Effects

In this paper a comprehensive investigation of a novel device called split-gate silicon-on-insulator MOSFET (SPG SOI MOSFET) is proposed to reduce short-channel effects (SCEs). Studying the device has been done by analytical approach and simulation. In the proposed structure the gate is split into two parts. A voltage difference exists between the two parts. It is demonstrated that the surface potential in the channel region exhibits a step function. Some improvements are obtained on parameters such as SCEs, hot-carrier effect (HCE), and drain-induced barrier lowering (DIBL). The accuracy of the results obtained by use of the analytical model is verified by ATLAS device simulation software. The obtained results of the model are compared with those of the single-gate (SG) SOI MOSFET. The simulation results show that the SPG SOI MOSFET performance is superior.

scholarly journals New Method for Determination of Drain Saturation Voltage in Short Channel MOS Devices Between Liquid Helium to Room Temperature

2001 ◽  
Vol 24 (2) ◽  
pp. 129-134
Author(s):  
Y. Amhouche ◽  
A. El Abbassi ◽  
K. Raïs ◽  
E. Bendada ◽  
R. Rmaily
Keyword(s):  
Room Temperature ◽  
Impact Ionization ◽  
Ionization Rate ◽  
Channel Length ◽  
New Method ◽  
Short Channel ◽  
Mos Devices ◽  
Impact Ionization Rate ◽  
The Impact

A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based on measurements of the partial derivative of the impact ionization rate. The method has been tested using main of channel length MOSFET devices and compared with others methods.

Hot Carrier Effect in Self-Aligned In–Ga–Zn–O Thin-Film Transistors With Short Channel Length

2020 ◽  
Vol 67 (12) ◽  
pp. 5544-5551
Author(s):  
Nuri On ◽  
Bo Kyoung Kim ◽  
Sueon Lee ◽  
Eun Hyun Kim ◽  
Jun Hyung Lim ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Channel Length ◽  
Short Channel ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Hot Carrier Effect

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

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