CVD Cu Process Development and Integration for sub-0.18 µm Devices

1999 ◽  
Vol 564 ◽  
Author(s):  
Jiming Zhang ◽  
Dean Denning ◽  
Greg Braeckelmann ◽  
Greg Hamilton ◽  
J. J Lee ◽  
...  

AbstractThe advent of inlaid Cu interconnects has presented new challenges for the industry to fill high aspect ratio dual inlaid features. CVD Cu offers advantages for excellent step coverage and is a technique extendible for future generations of devices. We have developed a robust CVD Cu process and a CVD/PVD reflow integration scheme. In this paper, we present results of an extensive study on CVD Cu process development and integration. The effects of various precursors, carrier gases (H2, He and N2) and barrier layers including CVD TiN, PVD Ta, PVD TaN, PVD Ta-Si-N, and a hybrid barrier, on the CVD Cu film properties and device electrical properties are discussed. The extendibility and challenges of current CVD Cu processing will also be discussed.

2012 ◽  
Vol 472-475 ◽  
pp. 1451-1454
Author(s):  
Xue Hui Wang ◽  
Wu Tang ◽  
Ji Jun Yang

The porous Cu film was deposited on soft PVDF substrate by magnetron sputtering at different sputtering pressure. The microstructure and electrical properties of Cu films were investigated as a function of sputtering pressure by X-ray diffraction XRD and Hall effect method. The results show that the surface morphology of Cu film is porous, and the XRD revealed that there are Cu diffraction peaks with highly textured having a Cu-(220) or a mixture of Cu-(111) and Cu-(220) at sputtering pressure 0.5 Pa. The electrical properties are also severely influenced by sputtering pressure, the resistivity of the porous Cu film is much larger than that fabricated on Si substrate. Furthermore, the resistivity increases simultaneously with the increasing of Cu film surface aperture, but the resistivity of Cu film still decreases with the increasing grain size. It can be concluded that the crystal structure is still the most important factor for the porous Cu film resistivity.


2010 ◽  
Vol 1252 ◽  
Author(s):  
Alexandre Guiraud ◽  
Nicolas Breil ◽  
Mickaël Gros-Jean ◽  
Damien Deleruyelle ◽  
Gilles Micolau ◽  
...  

AbstractWe have investigated the integration of Hf-based material as Inter Poly Dielectric in flash memories devices. Electrical measurements showed the good properties of SiO2/HfO2/SiO2 stacks. We then interested to the impact of the thermal budget on this specific stack which induces changes in the electrical properties. XPS measurements suggests those changes are due to the presence of an Hf-silicate layer at the SiO2/HfO2 interface.


2002 ◽  
Vol 16 (01n02) ◽  
pp. 197-204 ◽  
Author(s):  
W. L. GOH ◽  
K. T. TAN ◽  
M. S. TSE ◽  
K. Y. LIU

A thin seed layer (usually deposited by PVD or CVD) is essential for the copper electroplating technology in ULSI metallizations. Electroless Cu deposition has been proposed as an alternative to the PVD or CVD Cu seed technology due to its conformal nature. The electroless (EL) Cu technology requires an activation or catalyzation (usually by HF/PdCl 2 solution) to initiate the deposition process. This paper reports on the effect of the HF/PdCl 2 activation on the electroless Cu film properties. The implications of the HF/PdCl2 activation method on electroless Cu role as seed layer for Cu electroplating are also discussed. Electroless Cu has a very conformal growth on the TiN/Ti substrate; with a deposition rate of 15 nm/min. Prolonged HF/PdCl 2 has a negative impact to the Cu (111) texture, roughness and resistivity. The RBS analysis show that only trace amount of Pd is incorporated into the electroless Cu film.


2011 ◽  
Vol 1283 ◽  
Author(s):  
Nicolo’ Chiodarelli ◽  
Annelies Delabie ◽  
Sugiura Masahito ◽  
Yusaku Kashiwagi ◽  
Olivier Richard ◽  
...  

ABSTRACTBecause of their superior electronic properties and bottom-up growth mode, Carbon Nanotubes (CNT) may offer a valid alternative for high aspect ratio vertical interconnects in future generations of microchips. For being successful, though, CNT based interconnects must reach sufficiently low values of resistance to become competitive with current W or Cu based technologies. This essentially means that CMOS compatible processes are needed to produce dense CNT shells of extremely high quality with almost ideal contacts. Moreover, their electrical properties must be preserved at every process step in the integration of CNT into vertical interconnect structures. In this work this latter aspect is analyzed by studying the changes in the electrical characteristics when encapsulating CNT into different oxides. Oxide encapsulation is often exploited to hold the CNT in place and to avoid snapping during a polishing step. On the other hand, oxide encapsulation can influence the properties of the grown CNT which are directly exposed to possibly harmful oxidative conditions. Two different deposition techniques and oxides were evaluated: Chemical Vapor Deposition (CVD) of SiO2 (reference) and Atomic Layer Deposition (ALD) of Al2O3 in less aggressive oxidizing conditions. The two processes were transferred to CNT interconnect test structures on 200mm wafers and electrically benchmarked. The CNT resistance was measured in function of the CNT length which allows the extraction and individual distinction of the resistive contributions of the CNT and the contacts. It is shown that the encapsulating SiO2 deposited by CVD degrades the resistance of CNT by altering their quality. Directions for future improvements have been identified and discussed.


2001 ◽  
Vol 695 ◽  
Author(s):  
Alex A. Volinsky ◽  
Meike Hauschildt ◽  
Joseph B. Vella ◽  
N.V. Edwards ◽  
Rich Gregory ◽  
...  

ABSTRACTCopper films of different thicknesses between 0.2 and 2 microns were electroplated on adhesion-promoting TiW and Ta barrier layers on <100> single crystal 6-inch silicon wafers. The residual stress was measured after each processing step using a wafer curvature technique employing Stoney's equation. Large gradients in the stress distributions were found across each wafer. Controlled Cu grain growth was achieved by annealing films at 350 C for 3 minutes in high vacuum. Annealing increased the average tensile residual stress by about 200 MPa for all the films, which is in agreement with stress-temperature cycling measurements.After aging for 1 year wafer stress mapping showed that the stress gradients in the copper films were alleviated. No stress discrepancies between the copper on Ta and TiW barrier layers could be found. However, X-ray pole figure analysis showed broad and shifted (111) texture in films on a TiW underlayer, whereas the (111) texture in Cu films on Ta is sharp and centered.


2019 ◽  
Vol 87 (3) ◽  
Author(s):  
Jan Sieber ◽  
John W. Hutchinson ◽  
J. Michael T. Thompson

Abstract This paper investigates the robustness against localized impacts of elastic spherical shells pre-loaded under uniform external pressure. We subjected a pre-loaded spherical shell that is clamped at its equator to axisymmetric blast-like impacts applied to its polar region. The resulting axisymmetric dynamic response is computed for increasing amplitudes of the blast. Both perfect shells and shells with axisymmetric geometric imperfections are analyzed. The impact energy threshold causing buckling is identified and compared with the energy barrier that exists between the buckled and unbuckled static equilibrium states of the energy landscape associated with the pre-loaded pressure. The extent to which the impact energy of the threshold blast exceeds the energy barrier depends on the details of its shape and width. Targeted blasts that approximately replicate the size and shape of the energy barrier buckling mode defined in the paper have an energy threshold that is only modestly larger than the energy barrier. An extensive study is carried out for more realistic Gaussian-shaped blasts revealing that the buckling threshold energy for these blasts is typically in the range of at least 10–40% above the energy barrier, depending on the pressure pre-load and the blast width. The energy discrepancy between the buckling threshold and energy barrier is due to elastic waves spreading outward from the impact and dissipation associated with the numerical integration scheme. Buckling is confined to the vicinity of the pole such that, if the shell is not shallow, the buckling thresholds are not strongly dependent on the location of the clamping boundary, as illustrated for a shell clamped halfway between the pole and the equator.


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