New MEMS Technology Using Multi-Layer NILC Poly-Si and NiSi Films

2001 ◽  
Vol 687 ◽  
Author(s):  
W. M. Cheung ◽  
C. F. Cheng ◽  
M. C. Poon ◽  
M. Qin ◽  
C. Y. Yuen ◽  
...  
Keyword(s):  
Lower Layer ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Thermal Oxide ◽  
Mems Technology ◽  
Polysilicon Layer ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Device Properties ◽  
Si Wafer

AbstractA novel MEMS technology using multi-layer poly-silicon (poly-Si) is proposed. The poly-Si film is formed from the new Nickel-Induced-Lateral-Crystallization (NILC) method and has very large grain (>10νm) and near crystal quality. 700 nm thermal oxide was grown on a Si wafer. 100 nm LPCVD amorphous Si was deposited and followed by a 50 Å Ni deposition. The a-Si was crystallized at 550°C for 65 hours and subsequent 800°C for 2 hours to form the first (lower) NILC poly-Si layer. N-channel TFTs were fabricated on the NILC polysilicon layer. The process was repeated and a second (upper) polysilicon layer and TFTs were formed on top of the first polysilicon layer.The lower polysilicon has slightly larger grains and better material quality. Thin-film- transistors (TFT) fabricated on the 3-dimensional (3-D) poly-Si layers have I-V characteristics similar to (>40%) silicon-on-insulator TFTs. While TFTs on lower layer have better mobility and device properties, TFTs on upper layer have better uniformity. The accumulated heating and other effects have also been studied.

Effect Of Nickel In Large Grain Poly-Si Film Formed By Nickel Induced Lateral Crystallization and New Grain Enhancement Method

2000 ◽  
Vol 609 ◽  
Author(s):  
W.Y. Chan ◽  
A.M. Myasnikov ◽  
M.C. Poon ◽  
C.Y. Yuen ◽  
P. G. Han ◽  
...  
Keyword(s):  
Low Cost ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Enhancement Method ◽  
Novel Method ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Novel Applications ◽  
Soi Substrates

ABSTRACTLarge grain poly-silicon film (poly-Si) with high material quality and uniformity can have numerous novel applications such as providing a low cost alternative to form silicon-on-insulator (SOI) substrates and a breakthrough technology to ultra-dense 3-dimensional multi-layer SOI like devices and circuits. Nickel Induced Lateral Crystallization (NILC) of amorphous Si (a-Si) has been studied intensively, yet the grains are still small (∼ 1 μm). Recently, we have reported a novel method by combining NILC and a new annealing (at above 900 °C) to form poly-Si film with very large grains ranging from 10 μm to 100 μm. The film has good quality and the TFTs formed are highly comparable to SOI TFTs. This work further reports the effect of Ni to the new large-grain poly-Si film.

Effects of Process Conditions on the Performance of Large Grain Poly-Silicon on Insulator (LPSOI) MOSFET for Advanced CMOS Applications

2001 ◽  
Vol 686 ◽  
Author(s):  
S. Shivani ◽  
K. L. Ng ◽  
C. F. Cheng ◽  
M. C. Poon ◽  
Mansun Chan
Keyword(s):  
Material Characterization ◽  
Annealing Temperature ◽  
Thin Film Transistor ◽  
Silicon On Insulator ◽  
Process Conditions ◽  
Polysilicon Layer ◽  
Formation Method ◽  
Lateral Crystallization ◽  
Process Annealing

AbstractEffects of process annealing temperature on Metal-Induced-Lateral-Crystallization (MILC) growth rate and quality of MILC polysilicon formed were studied. Raman spectrum analysis was employed for material characterization. MILC polysilicon layer, which was formed by applying an optimum annealing condition together with post high temperature annealing, could be used to fabricate Thin-Film-Transistor (TFT) with considerably electrical improvements. This reflected that good quality of the polysilicon layer. It is believed that the proposed MILC formation method can be empolyed to produce large grain polysilicon on insulator (LPSOI) for advanced devices and circuits' fabrication.

scholarly journals Fabrication of a Silicon Nanowire Solar Cell on a Silicon-on-Insulator Substrate

2019 ◽  
Vol 9 (5) ◽  
pp. 818 ◽  
Author(s):  
Shinya Kato ◽  
Yasuyoshi Kurokawa ◽  
Kazuhiro Gotoh ◽  
Tetsuo Soga
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Conversion Efficiency ◽  
Silicon Nanowire ◽  
Surface Recombination ◽  
Silicon On Insulator ◽  
Sinw Array ◽  
Amorphous Si ◽  
Insulator Substrate ◽  
Si Wafer

This study proposes metal-assisted chemical etching (MAE) as a facile method to fabricate silicon nanowire (SiNW) array structures, with high optical confinement for thin crystalline silicon solar cells. Conventional SiNW arrays are generally fabricated on Si wafer substrates. However, tests on conventional SiNW-based solar cells cannot determine whether the photo-current is derived from SiNWs or from the Si wafer. Herein, SiNW arrays were fabricated on a silicon-on-insulator substrate with a 10-μm-thick silicon layer for measuring the photocurrent of the SiNW only. The 9 μm-long p-type SiNW arrays were applied to a solar cell structure fabricated using an n-type H-doped amorphous Si layer, thereby confirming the photovoltaic effect. However, the device exhibited a conversion efficiency of 0.0017% because of a low short-circuit current (Jsc) and a low open-circuit voltage (Voc). The low Jsc resulted from a high series resistance and high absorption loss from the amorphous Si layer, whereas the low Voc resulted from the high surface recombination velocity of the SiNW array structure. Therefore, reducing the surface recombination of SiNW-based solar cells can improve their conversion efficiency.

Diffusion of Silicon Interstitials in thin Silicon Films on Insulator in Neutral and Oxidising Annealing Ambients

1997 ◽  
Vol 469 ◽  
Author(s):  
Guénolé C.M. Silvestre
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Annealing Treatment ◽  
Silicon On Insulator ◽  
Buried Oxide ◽  
Thermal Oxide ◽  
Good Crystalline Quality ◽  
Thin Silicon ◽  
Experimental Values ◽  
Fault Growth

ABSTRACTSilicon-On-Insulator (SOI) materials have emerged as a very promising technology for the fabrication of high performance integrated circuits since they offer significant improvement to device performance. Thin silicon layers of good crystalline quality are now widely available on buried oxide layers of various thicknesses with good insulating properties. However, the SOI structure is quite different from that of bulk silicon. This paper will discuss a study of point-defect diffusion and recombination in thin silicon layers during high temperature annealing treatment through the investigation of stacking-fault growth kinetics. The use of capping layers such as nitride, thin thermal oxide and thick deposited oxide outlines the diffusion mechanisms of interstitials in the SOI structure. It also shows that the buried oxide layer is a very good barrier to the diffusion of point defects and that excess silicon interstitials may be reincorporated at the top interface with the thermal oxide through the formation of SiO species. Finally, from the experimental values of the activation energies for the growth and the shrinkage of stacking-faults, the energy of interstitial creation is evaluated to be 2.6 eV, the energy for interstitial migration to be 1.8 eV and the energy of interstitial generation during oxidation to be 0.2 eV.

Grain Quality Enhancement of Nickel-Crystallized Polysilicon Film in Quantum-Wire-Like Structures

2001 ◽  
Vol 686 ◽  
Author(s):  
Hongmei Wang ◽  
Singh Jagar ◽  
N. Zhan ◽  
C. F. Cheng ◽  
M. C. Poon ◽  
...  
Keyword(s):  
High Temperature ◽  
Quantum Wire ◽  
Grain Quality ◽  
Small Dimension ◽  
Deep Submicron ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Polysilicon Film ◽  
Crystallization Procedure ◽  
Lateral Crystallization

AbstractMethods for forming high quality re-crystallizing polysilicon films are being actively studied due to their ability to provide significant improvement to polysilicon Thin-Film-Transistors (TFT). Recently, a simple Metal-Induced-Lateral-Crystallization (MILC) method with nickel, together with high temperature annealing, can result in single crystal like polysilicon film [1]. TFTs fabricated on this so-called Large-grain Silicon-On-Insulator (LPSOI) can achieve SOI MOSFET performance especially for making small dimension devices. This paper reports that the polysilicon grain quality can be further enhanced by crystallizing the polysilicon film into the shape of long-wire.The crystallization procedure started with a regular Nickel-Induced-Lateral-Crystallization (NILC) process at 560 °C as described in [1]. The film was then etched into narrow wires, which were parallel to the direction of nickel propagation. The NILC second anneal at 900 °C was then performed on these silicon wire. Through surface energy anisotropy stimulated grain expansion in the NILC high-temperature second annealing, enhanced grain quality beyond that on planar polysilicon film.Transistor fabricated on these wire is similar to gate-all-around structure as that of FinFET [2]. Much better scalability to the deep submicron region was observed for these wire transistors than regular planar TFTs formed on the same NILC film. Experimental results showed that a wide transistor formed by the parallel combination of the quantum wire transistors much higher current drive than a TFT on the same NILC film with equivalent width.

Photoluminescence (PL) and Optically Detected Magnetic Resonance (ODMR) Study of Visible Light Emission from Porous Si

1991 ◽  
Vol 256 ◽  
Author(s):  
P. A. Lane ◽  
L. S. Swanson ◽  
J. Shinar ◽  
S. Chumbley
Keyword(s):  
Light Emission ◽  
Porous Si ◽  
Temperature Dependent ◽  
X Band ◽  
Amorphous Si ◽  
Optically Detected ◽  
Increasing Temperature ◽  
Hydrogenated Amorphous ◽  
Visible Light Emission ◽  
Si Wafer

ABSTRACTThe photoluminescence (PL) and X-band ODMR of porous Si layers is described and discussed. The layers were prepared by anodizing the (100) face of a Si wafer at 20 mA/cm2 in 20% HF for 5 mai and passively soaking them in 36% HF for up to 10 hrs. The PL was broad and featureless, extending from ˜1.5 to ˜2.1 eV and peaking at 1.68 eV. Its intensity slightly increased upon cooling to 90 K, and then strongly decreased at lower temperatures. A ˜20 G wide asymmetric PL-enhancing ODMR was observed at g ˜2.0031 ±I 0.0009, which could be fit to a sum of two Gaussians. Their g-values were slightly temperature dependent. The ODMR intensity strongly decreased with increasing temperature, and was unobservable above ˜80 K. The results are compared to the optical properties of hydrogenated amorphous Si.

A Study on the Metal Induced Lateral Crystallization Behavior of Amorphous Silicon Thin Films

1996 ◽  
Vol 441 ◽  
Author(s):  
Byung-Il Lee ◽  
Kwang-Ho Kim ◽  
Won-Cheol Jeong ◽  
Pyung-Su Ahn ◽  
Jin-Wook Shin ◽  
...  
Keyword(s):  
Thin Films ◽  
Amorphous Silicon ◽  
Crystallization Behavior ◽  
Crystallization Rate ◽  
External Stress ◽  
Tem Analysis ◽  
Silicon Thin Films ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Si Films

AbstractBasic mechanisms for both Ni- and Pd-metal induced lateral crystallization (MILC) are investigated. For both cases, tiny silicides were formed under the metal deposited area, and propagated toward amorphous Si films leaving crystallized Si behind at temperatures as low as 500 °C. Ni-MILC was influenced by Pd such that the lateral crystallization rate was enhanced, and the temperature for the lateral crystallization was lowered to 450 °C. Through TEM analysis and external stress experiments, it was found that the enhancement of the lateral crystallization rate was closely related to the compressive stress generated by the formation of nearby Pd2Si.

Structural characterization of nanostructures grown by Ni metal induced lateral crystallization of amorphous-Si

2016 ◽  
Vol 119 (6) ◽  
pp. 065303 ◽  
Author(s):  
G. Z. Radnóczi ◽  
E. Dodony ◽  
G. Battistig ◽  
N. Vouroutzis ◽  
P. Kavouras ◽  
...  
Keyword(s):  
Structural Characterization ◽  
Amorphous Si ◽  
Lateral Crystallization
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