Effects of Process Conditions on the Performance of Large Grain Poly-Silicon on Insulator (LPSOI) MOSFET for Advanced CMOS Applications

2001 ◽  
Vol 686 ◽  
Author(s):  
S. Shivani ◽  
K. L. Ng ◽  
C. F. Cheng ◽  
M. C. Poon ◽  
Mansun Chan
Keyword(s):  
Material Characterization ◽  
Annealing Temperature ◽  
Thin Film Transistor ◽  
Silicon On Insulator ◽  
Process Conditions ◽  
Polysilicon Layer ◽  
Formation Method ◽  
Lateral Crystallization ◽  
Process Annealing

AbstractEffects of process annealing temperature on Metal-Induced-Lateral-Crystallization (MILC) growth rate and quality of MILC polysilicon formed were studied. Raman spectrum analysis was employed for material characterization. MILC polysilicon layer, which was formed by applying an optimum annealing condition together with post high temperature annealing, could be used to fabricate Thin-Film-Transistor (TFT) with considerably electrical improvements. This reflected that good quality of the polysilicon layer. It is believed that the proposed MILC formation method can be empolyed to produce large grain polysilicon on insulator (LPSOI) for advanced devices and circuits' fabrication.

New MEMS Technology Using Multi-Layer NILC Poly-Si and NiSi Films

2001 ◽  
Vol 687 ◽  
Author(s):  
W. M. Cheung ◽  
C. F. Cheng ◽  
M. C. Poon ◽  
M. Qin ◽  
C. Y. Yuen ◽  
...  
Keyword(s):  
Lower Layer ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Thermal Oxide ◽  
Mems Technology ◽  
Polysilicon Layer ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Device Properties ◽  
Si Wafer

AbstractA novel MEMS technology using multi-layer poly-silicon (poly-Si) is proposed. The poly-Si film is formed from the new Nickel-Induced-Lateral-Crystallization (NILC) method and has very large grain (>10νm) and near crystal quality. 700 nm thermal oxide was grown on a Si wafer. 100 nm LPCVD amorphous Si was deposited and followed by a 50 Å Ni deposition. The a-Si was crystallized at 550°C for 65 hours and subsequent 800°C for 2 hours to form the first (lower) NILC poly-Si layer. N-channel TFTs were fabricated on the NILC polysilicon layer. The process was repeated and a second (upper) polysilicon layer and TFTs were formed on top of the first polysilicon layer.The lower polysilicon has slightly larger grains and better material quality. Thin-film- transistors (TFT) fabricated on the 3-dimensional (3-D) poly-Si layers have I-V characteristics similar to (>40%) silicon-on-insulator TFTs. While TFTs on lower layer have better mobility and device properties, TFTs on upper layer have better uniformity. The accumulated heating and other effects have also been studied.

High Precision Physical Model for Nickel MILC

2002 ◽  
Vol 715 ◽  
Author(s):  
C. F. Cheng ◽  
W. M. Cheung ◽  
K. L. Ng ◽  
P. J. Chan ◽  
M. C. Poon ◽  
...  
Keyword(s):  
Growth Rate ◽  
Physical Model ◽  
Growth Mechanism ◽  
Annealing Temperature ◽  
Annealing Process ◽  
Impurity Distribution ◽  
Metal Impurity ◽  
Metal Diffusion ◽  
Polysilicon Layer ◽  
Lateral Crystallization

AbstractMechanism and growth rate of Metal-Induced-Lateral-Crystallization (MILC) with annealing temperature range from 550°C to 625°C were studied. Base on the MILC growth mechanism and effect of metal diffusion, a modeling on metal impurity distribution was developed. The modeling can be used to predict the distribution of metal impurity formed in the polysilicon layer after MILC annealing process. By applying the modeling, effects of annealing on the metal impurity distribution can be analyzed.

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

scholarly journals Experimental Investigation on Micro Deep Drawing of Stainless Steel Foils with Different Microstructural Characteristics

2021 ◽  
Vol 34 (1) ◽  
Author(s):  
Jingwei Zhao ◽  
Tao Wang ◽  
Fanghui Jia ◽  
Zhou Li ◽  
Cunlong Zhou ◽  
...  
Keyword(s):  
Stainless Steel ◽  
Deep Drawing ◽  
Annealing Temperature ◽  
Localized Deformation ◽  
Microstructural Characteristics ◽  
Height Profile ◽  
Annealing Temperatures ◽  
Micro Deep Drawing ◽  
Profile Distribution

AbstractIn the present work, austenitic stainless steel (ASS) 304 foils with a thickness of 50 µm were first annealed at temperatures ranging from 700 to 1100 ℃ for 1 h to obtain different microstructural characteristics. Then the effects of microstructural characteristics on the formability of ASS 304 foils and the quality of drawn cups using micro deep drawing (MDD) were studied, and the mechanism involved was discussed. The results show that the as-received ASS 304 foil has a poor formability and cannot be used to form a cup using MDD. Serious wrinkling problem occurs on the drawn cup, and the height profile distribution on the mouth and the symmetry of the drawn cup is quite non-uniform when the annealing temperature is 700 ℃. At annealing temperatures of 900 and 950 ℃, the drawn cups are both characterized with very few wrinkles, and the distribution of height profile, symmetry and mouth thickness are uniform on the mouths of the drawn cups. The wrinkling becomes increasingly significant with a further increase of annealing temperature from 950 to 1100 ℃. The optimal annealing temperatures obtained in this study are 900 and 950 ℃ for reducing the generation of wrinkling, and therefore improving the quality of drawn cups. With non-optimized microstructure, the distribution of the compressive stress in the circumferential direction of the drawn foils becomes inhomogeneous, which is thought to be the cause of the occurrence of localized deformation till wrinkling during MDD.

scholarly journals Structural and Magnetic Properties of Ni81Fe19Thin Film Grown on Si(001) Substrate via Single Graphene Layer

2015 ◽  
Vol 2015 ◽  
pp. 1-5 ◽  
Author(s):  
Gui-fang Li ◽  
Shibin Liu ◽  
Shanglin Yang ◽  
Yongqian Du
Keyword(s):  
Thin Films ◽  
Magnetic Properties ◽  
Vapor Deposition ◽  
Graphene Layer ◽  
Structural Investigation ◽  
Annealing Temperature ◽  
Chemical Vapor ◽  
Magnetic Thin Films ◽  
Structural And Magnetic Properties

We prepared magnetic thin films Ni81Fe19on single-crystal Si(001) substrates via single graphene layer through magnetron sputtering for Ni81Fe19and chemical vapor deposition for graphene. Structural investigation showed that crystal quality of Ni81Fe19thin films was significantly improved with insertion of graphene layer compared with that directly grown on Si(001) substrate. Furthermore, saturation magnetization of Ni81Fe19/graphene/Si(001) heterostructure increased to 477 emu/cm3with annealing temperatureTa=400°C, which is much higher than values of Ni81Fe19/Si(001) heterostructures withTaranging from 200°C to 400°C.

scholarly journals Bias Stress Stability of Solution-Processed Nano Indium Oxide Thin Film Transistor

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 111
Author(s):  
Rihui Yao ◽  
Xiao Fu ◽  
Wanwan Li ◽  
Shangxiong Zhou ◽  
Honglong Ning ◽  
...  
Keyword(s):  
Thin Film ◽  
Indium Oxide ◽  
Spin Coating ◽  
Glass Substrate ◽  
Annealing Temperature ◽  
Oxide Thin Film ◽  
Process Conditions ◽  
Hydroxyl Groups ◽  
Band Theory ◽  
Indium Oxide Thin Film

In this paper, the effects of annealing temperature and other process parameters on spin-coated indium oxide thin film transistors (In2O3-TFTs) were studied. The research shows that plasma pretreatment of glass substrate can improve the hydrophilicity of glass substrate and stability of the spin-coating process. With Fourier transform infrared (FT-IR) and X-ray diffraction (XRD) analysis, it is found that In2O3 thin films prepared by the spin coating method are amorphous, and have little organic residue when the annealing temperature ranges from 200 to 300 °C. After optimizing process conditions with the spin-coated rotating speed of 4000 rpm and the annealing temperature of 275 °C, the performance of In2O3-TFTs is best (average mobility of 1.288 cm2·V−1·s−1, Ion/Ioff of 5.93 × 106, and SS of 0.84 V·dec−1). Finally, the stability of In2O3-TFTs prepared at different annealing temperatures was analyzed by energy band theory, and we identified that the elimination of residual hydroxyl groups was the key influencing factor. Our results provide a useful reference for high-performance metal oxide semiconductor TFTs prepared by the solution method.

Erbium-Silicided Source/Drain Junction Formation by Rapid Thermal Annealing Technique for Decananometer-Scale Schottky Barrier Metal-Oxide-Semiconductor Field- Effect Transistors

2004 ◽  
Vol 810 ◽  
Author(s):  
Moongyu Jang ◽  
Yarkyeon Kim ◽  
Jaeheon Shin ◽  
Kyoungwan Park ◽  
Seongjae Lee
Keyword(s):  
Schottky Barrier ◽  
Annealing Temperature ◽  
Field Effect Transistors ◽  
Growth Conditions ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Oxide Interface ◽  
Silicide Growth ◽  
Stable Growth ◽  
Optimum Annealing Temperature

ABSTRACTThe stable growth conditions of erbium-silicide on silicon-on-insulator (SOI) are investigated considering annealing temperature, SOI and sputtered erbium thickness. From the sheet resistance measurement, X-ray diffraction and Auger electron spectroscopy analysis, the optimum annealing temperature is determined as 500°C. Also, for the stable growth of erbium- silicide on SOI, the sputtered erbium thickness should be less than 1.5 times of SOI thickness. As the SOI thickness decreases below this critical thickness, erbium-rich region is formed at the erbium-silicide and buried-oxide interface. By applying the optimized erbium-silicide growth conditions, 50-nm-gate-length n-type SB-MOSFET is manufactured, which shows the possible usage of erbium-silicide as the source and drain material in the n-type Schottky barrier MOSFETs for decananometer regime applications.

The Influence of the Carbonization Mechanisms on the Crystalline Quality of the Carbonization Layer for Heteroepitaxial Growth of 3C-SiC

2014 ◽  
Vol 778-780 ◽  
pp. 230-233
Author(s):  
Yukimune Watanabe ◽  
Tsuyoshi Horikawa ◽  
Kiichi Kamimura
Keyword(s):  
Diffusion Mechanism ◽  
Growth Direction ◽  
Crystalline Quality ◽  
Process Conditions ◽  
Heteroepitaxial Growth ◽  
Crystal Axis ◽  
Si Substrates ◽  
Selected Area Electron Diffraction ◽  
Better Than

The carbonized layer for a buffer layer strongly influences the crystalline quality of the 3C-SiC epitaxial films on the Si substrates. The growth mechanism of the carbonized layer strongly depended on the process conditions. The surface of silicon substrate was carbonized under the pressure of 7.8 × 10-3 Pa or 7.8 × 10-2 Pa in this research. Under the relatively low pressure of 7.8 × 10-3 Pa, the carbonized layer was grown by the epitaxial mechanism. The crystal axis of the carbonized layer grown under this pressure was confirmed to coincide with the crystal axis of the Si substrate from the results of the selected area electron diffraction (SAED) analysis. Under the relatively high pressure condition of 7.8 × 10-2 Pa, the carbonized layer was grown by the diffusion mechanism. The result of the SAED pattern and the XTEM image indicated that this layer consisted of small grainy crystals and their crystal axes inclined against the growth direction. It was confirmed that the crystalline quality of the SiC film deposited on the carbonized layer grown by the epitaxial mechanism is better than that deposited on the layer grown by the diffusion mechanism.

Sign in / Sign up

Export Citation Format

Share Document