Grain Quality Enhancement of Nickel-Crystallized Polysilicon Film in Quantum-Wire-Like Structures

2001 ◽  
Vol 686 ◽  
Author(s):  
Hongmei Wang ◽  
Singh Jagar ◽  
N. Zhan ◽  
C. F. Cheng ◽  
M. C. Poon ◽  
...  

AbstractMethods for forming high quality re-crystallizing polysilicon films are being actively studied due to their ability to provide significant improvement to polysilicon Thin-Film-Transistors (TFT). Recently, a simple Metal-Induced-Lateral-Crystallization (MILC) method with nickel, together with high temperature annealing, can result in single crystal like polysilicon film [1]. TFTs fabricated on this so-called Large-grain Silicon-On-Insulator (LPSOI) can achieve SOI MOSFET performance especially for making small dimension devices. This paper reports that the polysilicon grain quality can be further enhanced by crystallizing the polysilicon film into the shape of long-wire.The crystallization procedure started with a regular Nickel-Induced-Lateral-Crystallization (NILC) process at 560 °C as described in [1]. The film was then etched into narrow wires, which were parallel to the direction of nickel propagation. The NILC second anneal at 900 °C was then performed on these silicon wire. Through surface energy anisotropy stimulated grain expansion in the NILC high-temperature second annealing, enhanced grain quality beyond that on planar polysilicon film.Transistor fabricated on these wire is similar to gate-all-around structure as that of FinFET [2]. Much better scalability to the deep submicron region was observed for these wire transistors than regular planar TFTs formed on the same NILC film. Experimental results showed that a wide transistor formed by the parallel combination of the quantum wire transistors much higher current drive than a TFT on the same NILC film with equivalent width.

Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.


2017 ◽  
Vol 39 (4) ◽  
pp. 11-20
Author(s):  
A. A. Khalatov ◽  
A. S. Kovalenko ◽  
S. B. Reznik

The features of the release of the cooling air in the interscapular channel high temperature gas turbines at the film cooling are considered. Possibilities of its local distribution on contour of an entrance edge of the perforated blades are investigated. The presented calculations show that the substantial increase in the cooling efficiency can be attained due to channels of small dimension in the blade wall.  


2011 ◽  
Vol 20 (03) ◽  
pp. 471-484 ◽  
Author(s):  
LIANG ZUO ◽  
ROBERT GREENWELL ◽  
SYED K. ISLAM ◽  
M. A. HUQUE ◽  
BENJAMIN J. BLALOCK ◽  
...  

In recent years, increasing demand for hybrid electric vehicles (HEVs) has generated the need for reliable and low-cost high-temperature electronics which can operate at the high temperatures under the hood of these vehicles. A high-voltage and high temperature gate-driver integrated circuit for SiC FET switches with short circuit protection has been designed and implemented in a 0.8-micron silicon-on-insulator (SOI) high-voltage process. The prototype chip has been successfully tested up to 200°C ambient temperature without any heat sink or cooling mechanism. This gate-driver chip can drive SiC power FETs of the DC-DC converters in a HEV, and future chip modifications will allow it to drive the SiC power FETs of the traction drive inverter. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175ΰC. Successful operation of the chip at this temperature with or without minimal heat sink and without liquid cooling will help achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module.


2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Ricardo Cardoso Rangel ◽  
Katia R. A. Sasaki ◽  
Leonardo Shimizu Yojo ◽  
João Antonio Martino

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.


2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000096-000103
Author(s):  
Yoann Dusé ◽  
Fabien Laplace ◽  
Nicolas Joubert ◽  
Xavier Montmayeur ◽  
Noureddine Zitouni ◽  
...  

We present in this paper two new products for high-temperature, low-voltage (2.8V to 5.5V) power management applications. The first product is an original implementation of a monolithic low dropout regulator (XTR70010), able to deliver up to 1A at 230°C with less than 1V of dropout. This new voltage regulator can source an output current level up to 1.5A. The regulated output voltage can be selected among 32 preset values from 0.5V to 3.6V in steps of 100mV, or it can be obtained with a pair of external resistors. The circuit integrates complex analog and digital control blocks providing state of the art features such as UVLO protection, chip enable control, soft start-up and soft shut-down, hiccup short-circuit protection, customer selectable thermal shut-down, input power supply protection, output overshoot remover and stability over an extremely wide range of load capacitances. The circuit offers a fair ±2% absolute accuracy and is guaranteed latch-up free. The second product is an advanced high-temperature, low-power, digitally trimmable voltage reference (XTR75020). Thanks to a custom, 1-wire serial interface, the absolute precision and the temperature coefficient can be adjusted in order to obtain an accuracy better than 0.5% with a temperature coefficient bellow ±20ppm/°C. On-chip OTP memory for trimming of absolute value and temperature coefficient makes the circuit extremely accurate and almost insensitive to drifts over time and temperature. The circuit features a class AB output buffer able to source or sink up to 5mA and remains stable with any load capacitance up to 50μF. The XTR75020 has nine preset possible output voltages. The source and sink short circuit current always remains bellow 25mA. The quiescent current consumption is 300μA typical at 230°C while the standby current is, in all cases, under 20μA. Both devices are designed on a latch-up free silicon-on-insulator process.


2010 ◽  
Vol 2010 (HITEC) ◽  
pp. 000283-000288 ◽  
Author(s):  
B. Reese ◽  
R. Shaw ◽  
J. Hornberger ◽  
R. Schupbach ◽  
A. Lostetter

This paper discusses the development of a high temperature (i.e., 230 °C ambient) 100V–300V/15V 20W isolated power supply. The power supply is implemented using Silicon-Carbide (SiC) power switches, high-temperature silicon on insulator (HTSOI) control circuitry, as well as custom high temperature magnetics and packaging technology. The heart of this power supply is a custom-built PWM controller. The controller was built utilizing HTSOI component, which operate at temperatures as high as 300 °C. The developed power supply targets high ambient temperature environment applications and includes features such as housekeeping power supply, soft-start and under-voltage lockout. The power supply is packaged using a multi-chip module (MCM) packaging approach. A single layer power substrate and a multiple layer control substrate are used. Bare die devices are utilized to save space, reduce parasitic impedances, and increase temperature of operation and reliability. This paper provides details on the electrical and thermal design as well as fabrication and characterization of the power supply. Additionally, results of the full characterization of this power supply are provided; this includes temperature testing up to 230 °C, efficiency results, load transition behavior, output ripple, etc.


2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000245-000252 ◽  
Author(s):  
Bruce W. Ohme ◽  
Mark R. Larson

Initial test results have been previously reported for a high-temperature (225°C) 12-bit analog-to-digital converter (HTADC12) fabricated using a production high-temperature silicon-on-insulator (SOI) CMOS process and assembled in hermetically sealed ceramic packages (ref. 1). Reliability test results for the HTADC12 are presented including parametric and functional test results from 1500 hours of dynamic life test at 250°C as well 1000 temperature cycles from −65°C to 200°C. Results of post-stress wirebond, and die bond testing are also provided.


2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000251-000254
Author(s):  
S T Riches ◽  
C Johnston ◽  
M Sousa ◽  
P Grant

Silicon on Insulator (SOI) device technology is fulfilling a niche requirement for electronics that functions satisfactorily at operating temperatures of >200°C. Most of the reliability data on the high temperature endurance of the devices is generated on the device itself with little attention being paid to the packaging technology around the device. Similarly, most of the reliability data generated on high temperature packaging technologies uses testpieces rather than real devices, which restricts any conclusions on long term electrical performance. This paper presents results of high temperature endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 7,056 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C. Different die attach and wire bond options have been included in the study and the performance of multiplexers, transistors, bandgap voltage, oscillators and voltage regulators functional blocks have been characterised. This work formed part of the UPTEMP project which was set-up with support from UK Technology Strategy Board and the EPSRC. The project brought together a consortium of end-users (Sondex Wireline and Vibro-Meter UK), electronic module manufacturers (GE Aviation Systems Newmarket) and material suppliers (Gwent Electronic Materials and Thermastrate Ltd) with Oxford University-Materials Department, the leading UK high temperature electronics research centre.


2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.


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