Effect Of Nickel In Large Grain Poly-Si Film Formed By Nickel Induced Lateral Crystallization and New Grain Enhancement Method

2000 ◽  
Vol 609 ◽  
Author(s):  
W.Y. Chan ◽  
A.M. Myasnikov ◽  
M.C. Poon ◽  
C.Y. Yuen ◽  
P. G. Han ◽  
...  
Keyword(s):  
Low Cost ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Enhancement Method ◽  
Novel Method ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Novel Applications ◽  
Soi Substrates

ABSTRACTLarge grain poly-silicon film (poly-Si) with high material quality and uniformity can have numerous novel applications such as providing a low cost alternative to form silicon-on-insulator (SOI) substrates and a breakthrough technology to ultra-dense 3-dimensional multi-layer SOI like devices and circuits. Nickel Induced Lateral Crystallization (NILC) of amorphous Si (a-Si) has been studied intensively, yet the grains are still small (∼ 1 μm). Recently, we have reported a novel method by combining NILC and a new annealing (at above 900 °C) to form poly-Si film with very large grains ranging from 10 μm to 100 μm. The film has good quality and the TFTs formed are highly comparable to SOI TFTs. This work further reports the effect of Ni to the new large-grain poly-Si film.

SOI Formation from Amorphous Silicon by Novel Gain Enhancement Method

1999 ◽  
Vol 587 ◽  
Author(s):  
C.Y. Yuen ◽  
M.C. Poon ◽  
M. Chan ◽  
M. Qin ◽  
W.Y. Chan ◽  
...  
Keyword(s):  
Thin Film Transistors ◽  
Low Cost ◽  
New Technology ◽  
Nickel Metal ◽  
Gain Enhancement ◽  
Enhancement Method ◽  
Good Potential ◽  
Lateral Crystallization ◽  
Novel Applications ◽  
Soi Substrates

AbstractLarge grain (> 10 um) poly-Si film has been formed from nickel Metal Induced Lateral Crystallization (MILC) and subsequent high temperature annealing. The fabricated thin film transistors (TFT) have near SOI performance. The new technology has good potential to provide low cost SOI substrates, multi-layer devices and other novel applications.

New MEMS Technology Using Multi-Layer NILC Poly-Si and NiSi Films

2001 ◽  
Vol 687 ◽  
Author(s):  
W. M. Cheung ◽  
C. F. Cheng ◽  
M. C. Poon ◽  
M. Qin ◽  
C. Y. Yuen ◽  
...  
Keyword(s):  
Lower Layer ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Thermal Oxide ◽  
Mems Technology ◽  
Polysilicon Layer ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Device Properties ◽  
Si Wafer

AbstractA novel MEMS technology using multi-layer poly-silicon (poly-Si) is proposed. The poly-Si film is formed from the new Nickel-Induced-Lateral-Crystallization (NILC) method and has very large grain (>10νm) and near crystal quality. 700 nm thermal oxide was grown on a Si wafer. 100 nm LPCVD amorphous Si was deposited and followed by a 50 Å Ni deposition. The a-Si was crystallized at 550°C for 65 hours and subsequent 800°C for 2 hours to form the first (lower) NILC poly-Si layer. N-channel TFTs were fabricated on the NILC polysilicon layer. The process was repeated and a second (upper) polysilicon layer and TFTs were formed on top of the first polysilicon layer.The lower polysilicon has slightly larger grains and better material quality. Thin-film- transistors (TFT) fabricated on the 3-dimensional (3-D) poly-Si layers have I-V characteristics similar to (>40%) silicon-on-insulator TFTs. While TFTs on lower layer have better mobility and device properties, TFTs on upper layer have better uniformity. The accumulated heating and other effects have also been studied.

A Novel Back-Reflecting UV-Assisted Metal-Induced Crystallization of Silicon on Glass

2001 ◽  
Vol 664 ◽  
Author(s):  
Leila Rezaee ◽  
Shamsoddin Mohajerzadeh ◽  
Ali Khakifirooz ◽  
Saber Haji ◽  
Ebrahim Asl Soleimani
Keyword(s):  
Silicon Film ◽  
Crystallization Rate ◽  
Ultra Violet ◽  
Hole Mobility ◽  
Metal Induced Crystallization ◽  
Polysilicon Films ◽  
Novel Method ◽  
Uv Photons ◽  
Lateral Crystallization ◽  
Induced Crystallization

ABSTRACTA novel method of UV-assisted metal-induced-crystallization is introduced to grow polysilicon films on ordinary glass at temperatures as low as 400°C. Annealing is accomplished in the presence of an ultra-violet exposure, leading to high crystallinity of the silicon film as confirmed by XRD, TEM and SEM analyses. A back-reflecting chromium layer is incorporated to further trap UV photons and enhance their absorption in the silicon film. This results in a significant increase in the crystallization rate as studied by XRD spectroscopy. A growth rate of 2 µm/hr is observed at 400 °C, when employing this method for lateral crystallization. Thin-film transistors fabricated using the proposed UV-assisted MILC show a threshold voltage of 1V and hole mobility of about 50 cm2/V.s.

The Effects of Annealing Temperature on the Characteristics of Buried Oxide Silicon-On-Insulator

1985 ◽  
Vol 53 ◽  
Author(s):  
B.-Y Mao ◽  
P.-H. Chang ◽  
H.W. Lam ◽  
B.W. Shen ◽  
J.A. Keenan
Keyword(s):  
Annealing Temperature ◽  
Silicon Film ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Thermal Donor ◽  
Buried Oxide ◽  
Lower Oxygen ◽  
Higher Temperature ◽  
Soi Substrates ◽  
Post Implantation

ABSTRACTThe effects of post implantation annealing on the properties of buried oxide silicon-on-insulator (SOI) substrates in the temperature range of 1150°C to 1300°C have been studied. Microstructural analyses showed that the crystallinity of the top silicon layer was improved at higher annealing temperature. Lower thermal donor generation at 450°C was observed in SOI annealed at higher temperature. The improvement in microstructure and lower thermal donor generation were correlated to the lower oxygen concentration in the top silicon film.

Polycrystalline Silicon Grown on Porous Silicon-on-Insulator Substrates

1996 ◽  
Vol 452 ◽  
Author(s):  
Klaus Y.J. Hsu ◽  
C. H. Lee ◽  
C. C. Yeh
Keyword(s):  
Porous Silicon ◽  
Low Temperature ◽  
Silicon Film ◽  
Silicon Layer ◽  
Porous Silicon Layer ◽  
Silicon On Insulator ◽  
Cross Sectional ◽  
Diffraction Patterns ◽  
Si Films ◽  
Soi Substrates

AbstractInexpensive full-wafer SOI substrates are appealing for various applications such as ULSI. As an attempt to achieve this goal, low-temperature deposition of silicon on novel porous Si-on-insulator (PSOI) substrates was performed in this work. The bottom insulator was obtained by anodically oxidizing a pre-formed porous silicon film in HCl solution. The thickness, uniformity and quality of the resulted bottom oxide layer as well as the residual porous silicon layer above were well-controlled. Low-temperature PECVD growth of silicon on the PSOI wafer was conducted by using the residual porous silicon as the seed. Cross-sectional TEM pictures and electron diffraction patterns showed that poly-Si films were formed on PSOI substrates under the conditions of 98% hydrogen dilution ratio, 20 Watts RF power, and 300°C substrate temperature. Further thermal annealing at 1050°C for 30 minutes significantly enhanced the crystallinity of the deposited films. Combined with the excellent insulation ability of the bottom oxide, the technique is suitable for future inexpensive full-wafer SOI fabrication.

Effect of Ramp Annealing to Ni Induced Lateral Crystallization of Amorphous Silicon

2000 ◽  
Vol 609 ◽  
Author(s):  
S. Shivani ◽  
M.C. Poon ◽  
M. Chan ◽  
P.K. Ko
Keyword(s):  
Grain Size ◽  
Amorphous Silicon ◽  
High Performance ◽  
Low Cost ◽  
New Technology ◽  
Silicon On Insulator ◽  
Effect Of Temperature ◽  
Process Time ◽  
Nickel Metal ◽  
Lateral Crystallization

ABSTRACTNickel Metal-Induced-Lateral-Crystallization (MILC) has been used to enlarge the grain size and improve the quality of (poly-Si) Thin-Film-Transistors (TFTs). However, the MILC temperature is still low and the grain size is still small. The feasibility of forming very large grains (single crystal like) from amorphous silicon (a-Si) by combining MILC with ramp annealing has been studied. It has been found that the grain size after ramp annealing is remarkably enhanced and can reach of the order of several ten's of microns. The velocity of MILC with ramp annealing is faster than that of MILC with isothermal annealing. The grain size becomes maximal at around 625°C/2hrs, and saturates at higher temperatures of 625- 1000°C. The effect of temperature, time and other parameters has also been studied in order to maximize the grain size and quality. MILC with ramp annealing at 625°C can greatly lower the process time and reduce the need of subsequent annealing to enhance the grain size. The new technology can have numerous novel applications such as providing a low cost alternative to form silicon-on-insulator (SOI) substrates and a breakthrough for high performance TFTs and novel multi-layers SOI like devices and circuits.

scholarly journals Imaging coronary plaques using 3D motion-compensated [18F]NaF PET/MR

2021 ◽  
Author(s):  
Johannes Mayer ◽  
Thomas-Heinrich Wurster ◽  
Tobias Schaeffter ◽  
Ulf Landmesser ◽  
Andreas Morguet ◽  
...  
Keyword(s):  
Attenuation Correction ◽  
Free Breathing ◽  
Cardiac Motion ◽  
Water Fraction ◽  
3 Dimensional ◽  
Background Ratio ◽  
Motion Models ◽  
Physiological Motion ◽  
Atherosclerosis Imaging ◽  
Novel Applications

Abstract Background Cardiac PET has recently found novel applications in coronary atherosclerosis imaging using [18F]NaF as a radiotracer, highlighting vulnerable plaques. However, the resulting uptakes are relatively small, and cardiac motion and respiration-induced movement of the heart can impair the reconstructed images due to motion blurring and attenuation correction mismatches. This study aimed to apply an MR-based motion compensation framework to [18F]NaF data yielding high-resolution motion-compensated PET and MR images. Methods Free-breathing 3-dimensional Dixon MR data were acquired, retrospectively binned into multiple respiratory and cardiac motion states, and split into fat and water fraction using a model-based reconstruction framework. From the dynamic MR reconstructions, both a non-rigid cardiorespiratory motion model and a motion-resolved attenuation map were generated and applied to the PET data to improve image quality. The approach was tested in 10 patients and focal tracer hotspots were evaluated concerning their target-to-background ratio, contrast-to-background ratio, and their diameter. Results MR-based motion models were successfully applied to compensate for physiological motion in both PET and MR. Target-to-background ratios of identified plaques improved by 7 ± 7%, contrast-to-background ratios by 26 ± 38%, and the plaque diameter decreased by −22 ± 18%. MR-based dynamic attenuation correction strongly reduced attenuation correction artefacts and was not affected by stent-related signal voids in the underlying MR reconstructions. Conclusions The MR-based motion correction framework presented here can improve the target-to-background, contrast-to-background, and width of focal tracer hotspots in the coronary system. The dynamic attenuation correction could effectively mitigate the risk of attenuation correction artefacts in the coronaries at the lung-soft tissue boundary. In combination, this could enable a more reproducible and reliable plaque localisation.

scholarly journals A Novel Method for Precise Guided Hole Fabrication of Dental Implant Surgical Guide Fabricated with 3D Printing Technology

2020 ◽  
Vol 11 (1) ◽  
pp. 49
Author(s):  
Keunbada Son ◽  
Kyu-Bok Lee
Keyword(s):  
3D Printing ◽  
Dental Implant ◽  
Present Report ◽  
Free Software ◽  
3D Printer ◽  
Printing Technology ◽  
Surgical Guide ◽  
3 Dimensional ◽  
3D Printing Technology ◽  
Novel Method

A dental implant surgical guide fabricated by 3-dimensional (3D) printing technology is widely used in clinical practice due to its convenience and fast fabrication. However, the 3D printing technology produces an incorrect guide hole due to the shrinkage of the resin materials, and in order to solve this, the guide hole is adjusted using a trimmer or a metal sleeve is attached to the guide hole. These methods can lead to another inaccuracy. The present method reports a technique to compensate for a decreased guide hole caused by shrinkage that can occur when a computer-guided implant surgical guide is fabricated with a 3D printer. The present report describes a technique to adjust the size of the guide hole using a free software program to identify the optimized guide hole size that is fabricated with the 3D printer.

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  
Keyword(s):  
Structural Properties ◽  
Solid Phase ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Defect Band ◽  
Future Technology ◽  
Ultrashallow Junctions ◽  
P Type ◽  
Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Engineering silicon-on-insulator (SOI) substrates for hybrid orientation technologies (HOT)

2009 ◽  
Author(s):  
T. Signamarcheix ◽  
B. Biasse ◽  
A-M. Papon ◽  
E. Nolot ◽  
B. Ghyselen ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Soi Substrates
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