Improvement of Gate Oxide Integrity in Low Temperature Poly Silicon TFT

2003 ◽  
Vol 762 ◽  
Author(s):  
Seok-Woo Lee ◽  
Dae Hyun Nam ◽  
Jin Mo Yoon ◽  
Hyun Sik Seo ◽  
Kyoung Moon Lim ◽  
...  
Keyword(s):  
Elevated Temperature ◽  
Deep Level ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Electrical Characteristics ◽  
Subthreshold Slope ◽  
Mos Capacitors ◽  
Oxide Charge ◽  
Oxide Deposition ◽  
Gate Oxide Integrity

AbstractThe electrical characteristics of SiH4-based PECVD gate oxide have been investigated with respect to gate oxide integrity (GOI) and its reliability. It was found that the GOI of poly-Si TFT integrated on glass substrate strongly depended on the charge trapping and deep level interface states generation under Fowler-Nordheim stress (FNS). By applying elevated temperature postanneal without vacuum break after the gate oxide deposition, highly reliable gate oxide was obtained. Under FNS, ID-VG curve showed severe shift and degradation of subthreshold slope, which were reduced by adopting post-annealed gate oxide. Besides, the TFT with post-annealed gate oxide showed around 10 times higher charge to breakdown than that of as-deposited gate oxide. Charge to breakdown of MOS capacitors were also studied. By applying post-annealed gate oxide, charge to breakdown drastically improved, which could be explained by reduced charge trapping under FNS.

SiC and GaN MOS Interfaces – Similarities and Differences

2010 ◽  
Vol 645-648 ◽  
pp. 473-478 ◽  
Author(s):  
T. Paul Chow
Keyword(s):  
Carrier Concentration ◽  
Threshold Voltage ◽  
Field Effect ◽  
Gate Oxide ◽  
Electron Trapping ◽  
Electrical Characteristics ◽  
Subthreshold Slope ◽  
Field Effect Mobility ◽  
Mos Capacitors ◽  
Similarities And Differences

We have comparatively characterized the electrical characteristics of 4H-SiC and 2H-GaN MOS capacitors and FETs. While progressive refinement of gate oxide processes, notably with NO anneal, has resulted in better threshold voltage control, reduced subthreshold slope and higher field-effect mobility for 4H-SiC MOSFETs, we have recently reported more superior MOS parameters for 2H-GaN MOSFETs. In addition, we have performed MOS-gated Hall measurements to extract the intrinsic carrier concentration and MOS mobility, indicating that both less channel electron trapping and scattering take place in 2H-GaN MOSFETs.

Improved SiO2/ 4H-SiC Interface Defect Density Using Forming Gas Annealing

2019 ◽  
Vol 963 ◽  
pp. 465-468
Author(s):  
Stephan Wirths ◽  
Giovanni Alfieri ◽  
Alyssa Prasmusinto ◽  
Andrei Mihaila ◽  
Lukas Kranz ◽  
...  
Keyword(s):  
Defect Density ◽  
Deep Level ◽  
Flat Band ◽  
Temperature Dependent ◽  
Mos Capacitors ◽  
Interface Defect ◽  
Before And After ◽  
Oxide Deposition ◽  
Transient Spectroscopy ◽  
Post Deposition

We investigated the influence of forming gas annealing (FGA) before and after oxide deposition on the SiO2/4H-SiC interface defect density (Dit). For MOS capacitors (MOSCAPs) that were processed using FGAs at temperatures above 1050°C, CV characterization revealed decreased flat band voltage shifts and stretch-out for different sweep directions and frequencies. Moreover, constant-capacitance deep level transient spectroscopy (CC-DLTS) was performed and showed Dit levels below 1012 cm-2eV-1 for post deposition FGA at 1200°C. Finally, lateral MOSFETs were fabricated to analyze the temperature-dependent threshold voltage (Vth) shift.

Reduced charge trapping in GaN MIS using gate oxide deposition technique

2009 ◽  
Vol 45 (10) ◽  
pp. 527
Author(s):  
T. Sreenidhi ◽  
K. Baskar ◽  
A. DasGupta ◽  
N. DasGupta
Keyword(s):  
Charge Trapping ◽  
Gate Oxide ◽  
Deposition Technique ◽  
Oxide Deposition

Optimization of 4H-SiC MOS Properties with Cesium Implantation

2008 ◽  
Vol 600-603 ◽  
pp. 751-754 ◽  
Author(s):  
Y. Wang ◽  
T. Khan ◽  
T. Paul Chow
Keyword(s):  
Low Frequency ◽  
Conduction Band Edge ◽  
Electrical Characteristics ◽  
Mos Capacitors ◽  
Oxide Charge ◽  
Charge Densities ◽  
Effective Oxide Charge ◽  
Flatband Voltage ◽  
State Densities ◽  
Interfacial State

The effect of incorporation of cesium with implantation on the electrical characteristics of SiO2/4H-SiC interface has been evaluated using MOS capacitors. With a cesium dosage of 1012 and 3x1012 cm-2 on deposited oxide re-oxidized in steam, effective oxide charge densities of - 1.4x1012 and -7.5x1011 cm-2 respectively were extracted and a cesium implant activation percentage of 33% was estimated from flatband voltage shift. Also, corresponding interfacial state densities of 2.5x1013 and 1.8x1013 cm-2-eV-1 near the conduction band edge were extracted from High-Low frequency C-V technique, showing a decreasing Dit with increasing Cs dosage.

Failure Analysis for Gate Oxide Breakdown

2008 ◽  
Author(s):  
Xianfeng Chen ◽  
Ming Li ◽  
Qiang Guo ◽  
Kary Chien ◽  
YanBo Gao
Keyword(s):  
Failure Analysis ◽  
Substrate Surface ◽  
Gate Oxide ◽  
Surface Damage ◽  
Process Window ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Oxide Breakdown ◽  
Oxide Deposition ◽  
Process Issue

Abstract Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.

Solutions to Gate Oxide Integrity on TFSOI Substrates Caused by PMOS Threshold-Voltage Implant

1998 ◽  
Vol 510 ◽  
Author(s):  
S. Q. Hong ◽  
T. Wetteroth ◽  
S. R. Wilson ◽  
B. Steele ◽  
D. K. Schroder
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Oxide Growth ◽  
Oxide Breakdown ◽  
Oxide Degradation ◽  
Process Damage ◽  
Gate Oxide Integrity

AbstractDue to the lack of effective gettering, gate oxide on thin-film-silicon-on-insulator (TFSOI) substrates is much more sensitive than its bulk Si counterpart to process damage during device fabrication, especially prior to gate oxide growth. Presented in this paper as a typical example is the severe oxide degradation caused by PMOS threshold-voltage implant. Several approaches to circumvent this problem are explored, such as Vt implant without sacrificial oxide (sacox), low temperature anneal before sacox removal, or implementation of lateral gettering. As a result of these efforts, a significant improvement in gate oxide integrity is achieved with increased oxide breakdown voltages and charge-to-breakdowns, as well as a reduction in oxide charge trapping. This work also demonstrates the feasibility of achieving bulk-comparable gate oxide on TFSOI substrates.

scholarly journals Characterization of SiO2/SiC Interfaces Annealed in N2O or POCl3

2014 ◽  
Vol 778-780 ◽  
pp. 623-626 ◽  
Author(s):  
Patrick Fiorenza ◽  
Lukas K. Swanson ◽  
Marilena Vivona ◽  
Filippo Giannazzo ◽  
Corrado Bongiorno ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Annealing Process ◽  
Electrical Behaviour ◽  
Electrical Parameters ◽  
Temperature Behaviour ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Oxide Deposition ◽  
Notable Increase

This paper reports a comparative characterization of SiO2/SiC interfaces subjected to post-oxide-deposition annealing in N2O or POCl3. Annealing process of the gate oxide in POCl3 allowed to achieve a notable increase of the MOSFET channel mobility (up to 108 cm2V-1s-1) with respect to the N2O annealing (about 20 cm2V-1s-1), accompanied by a different temperature behaviour of the electrical parameters in the two cases. Structural and compositional analyses revealed a different surface morphology of the oxide treated in POCl3, as a consequence of the strong incorporation of phosphorous inside the SiO2 matrix during annealing. This latter explained the instability of the electrical behaviour of MOS capacitors annealed in POCl3.

Characterization of Near-Interface Traps at Dielectric/SiC Interfaces Using CCDLTS

2019 ◽  
Vol 963 ◽  
pp. 217-221
Author(s):  
Isanka Jayawardhena ◽  
Asanka Jayawardena ◽  
Chun Kun Jiao ◽  
Dallas Morisette ◽  
Sarit Dhar
Keyword(s):  
Deep Level ◽  
Charge Trapping ◽  
Mos Capacitors ◽  
Dielectric Interfaces ◽  
Oxide Traps ◽  
The Difference ◽  
Transient Spectroscopy ◽  
Sic Wafer ◽  
First Time

Charge trapping at 4H-SiC/dielectric interfaces in 4H-SiC MOS capacitors has been investigated using constant capacitance deep level transient spectroscopy (CCDLTS). The experiments were focused on further understanding of the following aspects related to 4H-SiC/SiO2 interfaces: (i) Origin of near interface oxide traps (NITs), (ii) Effect of interfacial impurity/passivation methods and (iii) Characterization of near-interface oxide traps for different SiC wafer orientations. For the (0001) Si-face 4H-SiC/ SiO2 interface, two types of NITs are typically detected by CCDLTS, named ‘O1’ and ‘O2’ traps with emission activation energies of about 0.15±0.05 eV and 0.39±0.1 eV respectively below the 4H-SiC conduction band. Based on comparison with previous ab initio calculations, the physical identities of these defects have been suggested to be carbon dimers substituted for O dimers (‘O1’) and interstitial silicon atoms (‘O2’) in the near interfacial SiO2 respectively. In this work, it is shown for the first time that such traps are not observed for 4H-SiC/ Al2O3 interfaces, proving that these traps are inherent to the near-interfacial SiO2. In addition, the summary of CCDLTS results for Si-face with different interface trap passivation methods are included in this study. Finally, a comparison is presented for NO annealed (0001) Si-face, (11-20) a-face and (000-1) C-face interfaces that highlight the difference of CCDLTS signatures for the different crystal faces.

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