Failure Analysis for Gate Oxide Breakdown

2008 ◽  
Author(s):  
Xianfeng Chen ◽  
Ming Li ◽  
Qiang Guo ◽  
Kary Chien ◽  
YanBo Gao
Keyword(s):  
Failure Analysis ◽  
Substrate Surface ◽  
Gate Oxide ◽  
Surface Damage ◽  
Process Window ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Oxide Breakdown ◽  
Oxide Deposition ◽  
Process Issue

Abstract Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Thick Oxide Layers on N and P SiC Wafers by a Depo-Conversion Technique

1999 ◽  
Vol 572 ◽  
Author(s):  
Q. Zhang ◽  
V. Madangarli ◽  
I. Khlebnikov ◽  
S. Soloviev ◽  
T. S. Sudarshan
Keyword(s):  
Electrical Properties ◽  
Effective Charge ◽  
High Frequency ◽  
Breakdown Field ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Oxide Layers ◽  
Oxide Breakdown ◽  
Thermal Oxide ◽  
Capacitance Voltage

ABSTRACTThe electrical properties of thick oxide layers on n and p-type 6H-SiC obtained by a depoconversion technique are presented. High frequency capacitance-voltage measurements on MOS capacitors with a ∼ 3000 Å thick oxide indicates an effective charge density comparable to that of MOS capacitors with thermal oxide. The breakdown field of the depo-converted oxide obtained using a ramp response technique indicates a good quality oxide with average values in excess of 6 MV/cm on p-type SiC and 9 MV/cm on n-type SiC. The oxide breakdown field was observed to decrease with increase in MOS capacitor diameter.

The Effect of Silicide Formation on the Electrical Properties of Gate Oxides

1992 ◽  
Vol 260 ◽  
Author(s):  
J. P. Gambino ◽  
B. Cunningham ◽  
D. A. Buchanan
Keyword(s):  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Rapid Thermal Anneal ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Current Voltage ◽  
Capacitance Voltage

ABSTRACTCoSi2, or TiSi2 formation on gate polysilicon can degrade the current-voltage and capacitance-voltage characteristics of MOS capacitors. Degradation of the gate oxide breakdown field is much more severe for capacitors with TiSi2 than for those with COSi2 TEM reveals evidence for a reaction at the interface between TiSi2 and SiO2, whereas there is no observable reaction between COSi2 and SiO2- The low breakdown fields for devices with TiSi2 may be due to thinning of the gate oxide by the interfacial reaction or mechanical deformation. A high density of electron traps and a small reduction in the breakdown field is observed when COSi2 contacts the gate, possibly due to a compressive stress in the oxide exerted by the suicide. In addition, an increase in the interface state density at the Si-SiO2 interface is seen for all samples exposed to a rapid thermal anneal (RTA) at 800°C, possibly due to the release of H from dangling bonds.

Instability of Critical Electric Field in Gate Oxide Film of Heavy Ion Irradiated SiC MOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 673-676 ◽  
Author(s):  
Manato Deki ◽  
Takahiro Makino ◽  
Kazutoshi Kojima ◽  
Takuro Tomita ◽  
Takeshi Ohshima
Keyword(s):  
Silicon Carbide ◽  
Energy Transfer ◽  
Oxide Film ◽  
Electric Field ◽  
Ion Irradiation ◽  
Source Region ◽  
Gate Oxide ◽  
Heavy Ion ◽  
Mos Capacitors ◽  
Oxide Breakdown

The critical electric field (Ecr) of the gate oxide in 4H-Silicon Carbide (SiC) MOSFETs was measured under inversion bias conditions with ion irradiation. The Linear Energy Transfer (LET) dependence of theEcrat which the gate oxide breakdown occurred in these MOSFETs was evaluated. The linear relationship between theEcr-1andLETwas observed for SiC MOSFETs. The slope of theLET-1/Ecrfor SiC MOSFETs is almost the same that of theLET-1/Ecrlines for SiC MOS capacitors. TheVdsdependence ofEcrwas also evaluated. The correlation between the direction of electric field of drain-source region and direction of ion incidence affects to instability ofEcr.

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

2013 ◽  
Vol 740-742 ◽  
pp. 745-748 ◽  
Author(s):  
J. Sameshima ◽  
Osamu Ishiyama ◽  
Atsushi Shimozato ◽  
K. Tamura ◽  
H. Oshima ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Breakdown Region

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

scholarly journals Characterization of SiO2/SiC Interfaces Annealed in N2O or POCl3

2014 ◽  
Vol 778-780 ◽  
pp. 623-626 ◽  
Author(s):  
Patrick Fiorenza ◽  
Lukas K. Swanson ◽  
Marilena Vivona ◽  
Filippo Giannazzo ◽  
Corrado Bongiorno ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Annealing Process ◽  
Electrical Behaviour ◽  
Electrical Parameters ◽  
Temperature Behaviour ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Oxide Deposition ◽  
Notable Increase

This paper reports a comparative characterization of SiO2/SiC interfaces subjected to post-oxide-deposition annealing in N2O or POCl3. Annealing process of the gate oxide in POCl3 allowed to achieve a notable increase of the MOSFET channel mobility (up to 108 cm2V-1s-1) with respect to the N2O annealing (about 20 cm2V-1s-1), accompanied by a different temperature behaviour of the electrical parameters in the two cases. Structural and compositional analyses revealed a different surface morphology of the oxide treated in POCl3, as a consequence of the strong incorporation of phosphorous inside the SiO2 matrix during annealing. This latter explained the instability of the electrical behaviour of MOS capacitors annealed in POCl3.

ESD Failure Analysis and Robustness Design in Vertical-Diffused MOS Transistors

2014 ◽  
Vol 926-930 ◽  
pp. 456-461
Author(s):  
Shen Li Chen ◽  
Wen Ming Lee ◽  
Chi Ling Chu
Keyword(s):  
Failure Analysis ◽  
Oxide Layer ◽  
Failure Mode ◽  
Epitaxial Layer ◽  
Gate Oxide ◽  
The Other ◽  
Mos Transistors ◽  
Oxide Breakdown ◽  
Analysis Techniques ◽  
Silicon Epitaxial Layer

This paper deals with a detailed study of ESD failure mode and how to strengthen of the VDMOS used for power applications. The ESD post-zapped failure of power VDMOS transistors due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. The MM failure mode in this power MOSFET was caused by the gate oxide breakdown near n+ region in the source end as an ESD zapping. And, the ESD failure damage under HBM and CDM stresses were caused by the gate material molten near the gate pad and tunneled through the oxide layer into silicon epitaxial layer. Furthermore, the ESD robustness designs of power VDMOS transistors are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

Improvement of Gate Oxide Integrity in Low Temperature Poly Silicon TFT

2003 ◽  
Vol 762 ◽  
Author(s):  
Seok-Woo Lee ◽  
Dae Hyun Nam ◽  
Jin Mo Yoon ◽  
Hyun Sik Seo ◽  
Kyoung Moon Lim ◽  
...  
Keyword(s):  
Elevated Temperature ◽  
Deep Level ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Electrical Characteristics ◽  
Subthreshold Slope ◽  
Mos Capacitors ◽  
Oxide Charge ◽  
Oxide Deposition ◽  
Gate Oxide Integrity

AbstractThe electrical characteristics of SiH4-based PECVD gate oxide have been investigated with respect to gate oxide integrity (GOI) and its reliability. It was found that the GOI of poly-Si TFT integrated on glass substrate strongly depended on the charge trapping and deep level interface states generation under Fowler-Nordheim stress (FNS). By applying elevated temperature postanneal without vacuum break after the gate oxide deposition, highly reliable gate oxide was obtained. Under FNS, ID-VG curve showed severe shift and degradation of subthreshold slope, which were reduced by adopting post-annealed gate oxide. Besides, the TFT with post-annealed gate oxide showed around 10 times higher charge to breakdown than that of as-deposited gate oxide. Charge to breakdown of MOS capacitors were also studied. By applying post-annealed gate oxide, charge to breakdown drastically improved, which could be explained by reduced charge trapping under FNS.

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