Improved SiO2/ 4H-SiC Interface Defect Density Using Forming Gas Annealing

2019 ◽  
Vol 963 ◽  
pp. 465-468
Author(s):  
Stephan Wirths ◽  
Giovanni Alfieri ◽  
Alyssa Prasmusinto ◽  
Andrei Mihaila ◽  
Lukas Kranz ◽  
...  
Keyword(s):  
Defect Density ◽  
Deep Level ◽  
Flat Band ◽  
Temperature Dependent ◽  
Mos Capacitors ◽  
Interface Defect ◽  
Before And After ◽  
Oxide Deposition ◽  
Transient Spectroscopy ◽  
Post Deposition

We investigated the influence of forming gas annealing (FGA) before and after oxide deposition on the SiO2/4H-SiC interface defect density (Dit). For MOS capacitors (MOSCAPs) that were processed using FGAs at temperatures above 1050°C, CV characterization revealed decreased flat band voltage shifts and stretch-out for different sweep directions and frequencies. Moreover, constant-capacitance deep level transient spectroscopy (CC-DLTS) was performed and showed Dit levels below 1012 cm-2eV-1 for post deposition FGA at 1200°C. Finally, lateral MOSFETs were fabricated to analyze the temperature-dependent threshold voltage (Vth) shift.

Electron Trapping in 4H-SiC MOS Capacitors Fabricated by Sodium-Enhanced Oxidation

2012 ◽  
Vol 717-720 ◽  
pp. 757-760 ◽  
Author(s):  
Alberto F. Basile ◽  
A.C. Ahyi ◽  
L.C. Feldman ◽  
J.R. Williams ◽  
P.M. Mooney
Keyword(s):  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Electron Trapping ◽  
Stress Tests ◽  
Temperature Dependent ◽  
Mos Capacitors ◽  
Total Electron ◽  
Enhanced Oxidation ◽  
Transient Spectroscopy ◽  
Bias Temperature Stress

The electrical properties of the SiO2/SiC interface fabricated by sodium-enhanced oxidation (SEO) of n-type 4H-SiC were studied by temperature-dependent C-V and constant-capacitance deep level transient spectroscopy (CCDLTS). With the exception of near-interface traps in the SiC epi-layer, which are not present in the SEO samples, the trap species observed in SEO capacitors are the same as those observed in both standard-oxidized and NO-annealed MOS capacitors. Total electron trapping in accumulation is comparable in SEO and NO-annealed capacitors; however, the traps in SEO capacitors are located at the interface whereas tunneling into oxide traps is observed in NO-annealed samples. A series of bias-temperature stress tests show that electron trapping is essentially unchanged when mobile sodium ions are moved toward the interface. The improved mobility attained by this process compared to NO annealing may be due to the absence of near-interface SiC traps in SEO samples.

scholarly journals Влияние нейтронного облучения на спектр дефектов с глубокими уровнями в GaAs, изготовленном методом жидкофазной эпитаксии в атмосфере водорода и аргона

2022 ◽  
Vol 56 (1) ◽  
pp. 53
Author(s):  
М.М. Соболев ◽  
Ф.Ю. Солдатенков
Keyword(s):  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Experimental Studies ◽  
Shallow Donor ◽  
Defect Clusters ◽  
Deep Traps ◽  
Capacitance Voltage ◽  
Before And After ◽  
Transient Spectroscopy ◽  
Different Doses

The results of experimental studies of capacitance– voltage characteristics, spectra of deep-level transient spectroscopy of graded high-voltage GaAs p+−p0−i−n0 diodes fabricated by liquid-phase epitaxy at a crystallization temperature of 900C from one solution–melt due to autodoping with background impurities, in a hydrogen or argon ambient, before and after irradiation with neutrons. After neutron irradiation, deep-level transient spectroscopy spectra revealed wide zones of defect clusters with acceptor-like negatively charged traps in the n0-layer, which arise as a result of electron emission from states located above the middle of the band gap. It was found that the differences in capacitance–voltage characteristics of the structures grown in hydrogen or argon ambient after irradiation are due to different doses of irradiation of GaAs p+−p0−i−n0 structures and different degrees of compensation of shallow donor impurities by deep traps in the layers.

Transport Properties and Conduction Band Offset of n-ZnO/n-6H-SiC Heterostructures

2006 ◽  
Vol 957 ◽  
Author(s):  
Yahya Alivov ◽  
Xiao Bo ◽  
Fan Qian ◽  
Daniel Johnstone ◽  
Cole Litton ◽  
...  
Keyword(s):  
Conduction Band ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Band Offset ◽  
Measured Temperature ◽  
Temperature Dependent ◽  
Conduction Band Offset ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Transient Spectroscopy

ABSTRACTThe conduction band offset of n-ZnO/n-6H-SiC heterostructures fabricated by rf-sputtered ZnO on commercial n-type 6H-SiC substrates has been measured. Temperature dependent current-voltage characteristics, photocapacitance, and deep level transient spectroscopy measurements showed the conduction band offsets to be 1.25 eV, 1.1 eV, and 1.22 eV, respectively.

“Recovery” Effect of Electron Induced Damage in 4H-SiC Schottky Diodes

2003 ◽  
Vol 792 ◽  
Author(s):  
A. Castaldini ◽  
A. Cavallini ◽  
L. Rigutti ◽  
F. Nava ◽  
P.G. Fuochi ◽  
...  
Keyword(s):  
Deep Level ◽  
Collection Efficiency ◽  
Schottky Diodes ◽  
Chemical Vapour ◽  
Liquid Nitrogen Temperature ◽  
Charge Collection Efficiency ◽  
Before And After ◽  
Transient Spectroscopy ◽  
Lower Temperature ◽  
Different Doses

ABSTRACTThe effects of electron irradiation on the defects associated electronic levels in Schottky diodes on 4H silicon carbide epilayers grown by chemical vapour deposition were investigated by Deep Level Transient Spectroscopy (DLTS) and Capacitance-Voltage (C-V) characteristics. These investigations were performed before and after irradiation with 8.6 MeV electrons at different doses. After irradiation four new traps with enthalpies equal to (Ec-0.23 eV), (Ec-0.39 eV), (Ec-0.63 eV) and (Ec-0.75 eV) were detected. Their thermal stability, a key point to determine their structure on the basis of recent theoretical and experimental results, was carefully investigated since it was earlier observed that during DLTS temperature runs up to 500 K a slight but significant recovery of a few irradiation-induced levels occurs. This effect was previously observed in literature for the level (Ec-0.70 eV) after thermal treatment at 500 °C [1], but the present results indicate that it involves more than a single level and is also effective at lower temperature. DLTS analyses were also performed from room temperature to liquid nitrogen temperature and vice versa up to 500 K.The annealing kinetics is reported and a few conclusions on the structure of the defects involved in the recovery are drawn. The correlation with the diode charge collection efficiency is also reported.

Contact-Related Deep States in AI-GaInP/GaAs Interface

1993 ◽  
Vol 325 ◽  
Author(s):  
Z.C. Huang ◽  
C.R. Wie
Keyword(s):  
Deep Level ◽  
Schottky Diodes ◽  
Schottky Contact ◽  
Temperature Dependent ◽  
Current Voltage ◽  
Oxygen Contamination ◽  
Related Defect ◽  
Current Voltage Characteristics ◽  
Transient Spectroscopy ◽  
Recombination Current

AbstractDeep levels have been measured in molecular beam epitaxy grown Ga0.51In0.49P/GaAs heterostructure by double correlation deep level transient spectroscopy. Gold(Au) and Aluminum (Al) metals were used for Schottky contact. A contact-related hole trap with an activation energy of 0.50-0.75eV was observed at the A1/GaInP interface, but not at the Au/GaInP interface. To our knowledge, this contact-related trap has not been reported before. We attribute this trap to the oxygen contamination, or a vacancy-related defect, VIn or VGa. A new electron trap at 0.28eV was also observed in both Au- and Al-Schottky diodes. Its depth profile showed that it is a bulk trap in GaInP epilayer. The temperature dependent current-voltage characteristics (I-V-T) show a large interface recombination current at the GaInP surface due to the Al-contact. Concentration of the interface trap and the magnitude of recombination current are both reduced by a rapid thermal annealing at/or above 450°C after the aluminum deposition.

scholarly journals Designing a Robust Kelvin Probe Setup Optimized for Long-Term Surface Photovoltage Acquisition

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 4068 ◽  
Author(s):  
Elke Beyreuther ◽  
Stefan Grafström ◽  
Lukas Eng
Keyword(s):  
Deep Level ◽  
Surface Photovoltage ◽  
Probe Design ◽  
Relaxation Processes ◽  
Kelvin Probe ◽  
Electrical Stability ◽  
Temperature Dependent ◽  
Transient Spectroscopy ◽  
Photoinduced Charge

We introduce a robust low-budget Kelvin probe design that is optimized for the long-term acquisition of surface photovoltage (SPV) data, especially developed for highly resistive systems, which exhibit—in contrast to conventional semiconductors—very slow photoinduced charge relaxation processes in the range of hours and days. The device provides convenient optical access to the sample, as well as high mechanical and electrical stability due to off-resonance operation, showing a noise band as narrow as 1 mV. Furthermore, the acquisition of temperature-dependent SPV transients necessary for SPV-based deep-level transient spectroscopy becomes easily possible. The performance of the instrument is demonstrated by recording long-term SPV transients of the ultra-slowly relaxing model oxide strontium titanate (SrTiO 3 ) over 20 h.

Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide

2008 ◽  
Vol 600-603 ◽  
pp. 771-774 ◽  
Author(s):  
Ming Hung Weng ◽  
Rajat Mahapatra ◽  
Nicolas G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Elevated Temperatures ◽  
Gate Dielectric ◽  
Flat Band ◽  
Interface Properties ◽  
Temperature Dependent ◽  
Oxide Charge ◽  
Before And After ◽  
Mis Capacitors ◽  
The Ideal

The interface properties of TiO2/SiO2/SiC metal-insulator-semiconductor (MIS) capacitors were investigated by C-V and G-V measurements over a range of frequencies between 10 kHz and 1 MHz from room temperature up to 500°C. Ledges from multiple traps were observed during high frequency (1 MHz) sweeps from inversion to accumulation during measurements at elevated temperatures. The high measuring temperature resulted in the annealing of the sample, where the existence of trap ledges was observed to be temperature dependent. For n-type substrate negative Qf causes the shift of the C-V curve to more negative gate bias with respect to the ideal C-V curve. These fixed oxide charge is substantially reduced after post metallization annealing (PMA). We report the flat band voltage, detail in reducing fixed oxide charge and temperature dependence of density of interface traps before and after annealing of TiO2 high-κ gate dielectric stacks on a 4H-SiC based device.

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