Device Characteristics of Ultra-shallow Junctions Formed by fRTP Annealing

2004 ◽  
Vol 810 ◽  
Author(s):  
A. Satta ◽  
R. Lindsay ◽  
S. Severi ◽  
K. Henson ◽  
K. Maex ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Wafer Surface ◽  
Process Conditions ◽  
Device Performance ◽  
Correct Process ◽  
Leakage Currents ◽  
Dopant Activation ◽  
Junction Formation ◽  
Ultra Shallow Junctions ◽  
Limited Diffusion

ABSTRACTThe creation of ultra-shallow junction for CMOS devices at the sub-100 nm node is driving significant efforts in developing thermal processing to give rise to high dopant activation in combination with limited diffusion. Flash-assist Rapid Thermal Annealing™ (fRTP™) is a promising new annealing technique, which involves the heating of the bulk of the wafer to an intermediate temperature using rather conventional spike RTP, followed by a short and intense pulse of light localized on the implanted wafer surface.In this work, we have systematically investigated the junction formation of different implants under fRTP anneals in terms of profile and devices. Co-implanted Ge and F species provide more box-like profiles with improved activation. Although leakage currents are higher for fRTP-annealed junctions than for spike-annealed junctions, appropriate fRTP process parameters and correct process conditions provide a critical tool to control and reduce the leakage current of co-implanted fRTP junctions to acceptable levels. Proper implant and anneal are requested for minimizing pattern effect and improving device performance.

A 3-Dimensional Temperature Uniformity Model for a Rapid Thermal Processing Furnace

1994 ◽  
Vol 342 ◽  
Author(s):  
R. Henda ◽  
E. Scheid ◽  
D. Bielle-Daspet
Keyword(s):  
Thermal Processing ◽  
Three Dimensional ◽  
Wafer Surface ◽  
Process Conditions ◽  
Dimensional Model ◽  
Radiation Heat ◽  
Three Dimensional Model ◽  
3 Dimensional ◽  
Component Models ◽  
System Geometry

ABSTRACTA fully three dimensional model has been developed for simulating the thermal behaviour of a RTP furnace. This model consists of two components to achieve the whole analysis. The first component models the radiation heat flux density at the wafer surface as a function of the system geometry, the lamp position and intensity, and the wall reflectivities. The second component solves the heat conduction equation at each point within the wafer using appropriate boundary conditions, including convective cooling which effect depends on the process conditions. A particular attempt is made upon the achievement of a flat temperature profile over the wafer by investigating the system parameters in order to improve the RTP equipement.

Study of CoSix Spike Leakage for 0.1-um CMOS

2000 ◽  
Vol 611 ◽  
Author(s):  
Ken-ichi Goto
Keyword(s):  
Leakage Current ◽  
Process Conditions ◽  
Si Substrate ◽  
Leakage Currents ◽  
Junction Area ◽  
Atom Diffusion ◽  
Silicide Film ◽  
Leakage Model ◽  
Leakage Mechanism ◽  
Ultra Shallow Junctions

ABSTRACTWe have clarified a new leakage mechanism in Co salicide process for the ultra-shallow junctions of 0.1-um CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents generate from many localized points that are randomly distributed in the junction area, and not from the junction edge. We successfully verified our localized leakage model using Monte Carlo simulation. We identified abnormal CoSix spiking growth under the Co silicide film, as being the origin of the localized leakage current. These CoSix spikes grow rapidly only during annealing between 400°C and 450°C when Co2Si phase is formed. These spikes never grow during annealing at over 500°C, and decrease with high temperature annealing over 500°C. A minimum leakage current can be achieved by optimized annealing at between 800°C and 850°C for 30 sec. This is because a trade-off between reducing the CoSix spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900°C.

Ultra Shallow Junction Formation by RTA at High Temperature for Short Heating Cycle Time

1998 ◽  
Vol 532 ◽  
Author(s):  
S. Saito ◽  
S. Shishiguchi ◽  
A. Mineji ◽  
T. Matsuda
Keyword(s):  
Beam Current ◽  
Process Conditions ◽  
Key Factors ◽  
Enhanced Diffusion ◽  
Junction Formation ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions ◽  
Ion Species ◽  
Temperature Time ◽  
Short Heating

ABSTRACTIn accordance with decrease of device size, ultra shallow junctions are required for realizing superior device performance. Enhanced diffusion caused by implantation is a crucial factor to realize ultra shallow junctions. Not only implant but also RTA conditions are key factors to suppress enhanced diffusion. In this paper, process conditions to minimize enhanced diffusion are discussed. Implant ion species, energy, dose and beam current parameters are investigated for implantation and temperature, time and ramping rate parameters are investigated for RTA. Important result is that optimization of not only implant but also RTA conditions should be carried out in order to fabricate ultra shallow junctions.

Non-Equilibrium InSb/InAISb Diodes Grown by MBE

1997 ◽  
Vol 484 ◽  
Author(s):  
A D Johnson ◽  
A B J Smout ◽  
J W Cairns ◽  
G J Pryce ◽  
A J Pidduck ◽  
...  
Keyword(s):  
Room Temperature ◽  
Molecular Beam ◽  
Device Performance ◽  
Leakage Currents ◽  
Lower Growth ◽  
Dopant Activation ◽  
Atomic Force ◽  
Temperature Window ◽  
Lower Growth Temperature ◽  
Non Equilibrium

AbstractThe application of non-equilibrium transport techniques to Molecular Beam Epitaxy (MBE) grown InSb/InAlSb heterostructure diodes has produced practical devices such as midinfrared LED's and negative luminescent sources that operate at room temperature. By extending the epitaxial growth to vicinal InSb substrates it has been demonstrated that the temperature window for high quality epitaxy can be lowered by ∼12°C, giving greatly improved epilayer morphology. The degree of misorientation needed for given growth temperatures is shown from Atomic Force Microscope (AFM) measurements to be only ∼2°. In addition, the lower growth temperature gives improved dopant activation, lower trap densities and lower reverse bias leakage currents, with consequent benefits to device performance.

NMOS Performance of Low Boron Activation on Group V for Ultra-Shallow Junction Formation

2013 ◽  
Vol 716 ◽  
pp. 248-253
Author(s):  
Muzalifah Mohd Said ◽  
Zul Atfyi Fauzan Mohammed Napiah ◽  
Faiz Arith ◽  
Zarina Mohd Noh
Keyword(s):  
Computer Aided Design ◽  
Cmos Technology ◽  
Electrical Characteristics ◽  
Group V ◽  
Dopant Activation ◽  
Shallow Junction ◽  
Junction Formation ◽  
Chip Fabrication ◽  
Ultra Shallow Junctions ◽  
Aided Design

Fabrication of ultra shallow junctions with low contact resistances is desired to advance current CMOS technology. The low Boron activation on Group V for ultra shallow junction formation will makes the chip fabrication works effectively. SilvacoTCAD (Technology Computer Aided Design) manages simulation tasks and analyzing simulation results when ultra-shallow junction formation is using low-boron activation on Phosphorus, Antimony and Arsenic.A stimulate process like implantation, diffusion and dopant activation and epitaxial growth in different semiconductor materials has been analyzed as well as investigate the effects of energy of boron ion beams on ultra shallow junction formation.As a result, the electrical characteristics of NMOS structure by obtaining graph of IDVGSand IDVDShas been studied when there are variations in junction length (Xj), and gatelength (Lg).

Effect of Laser Thermal Processing on Defect Evolution in Silicon

2002 ◽  
Vol 717 ◽  
Author(s):  
Erik Kuryliw ◽  
Kevin S. Jones ◽  
David Sing ◽  
Michael J. Rendon ◽  
Somit Talwar
Keyword(s):  
Point Defects ◽  
Thermal Processing ◽  
Defect Formation ◽  
Secondary Ion Mass Spectrometry ◽  
Laser Energy ◽  
Process Window ◽  
Loop Formation ◽  
Transmission Electron ◽  
Ultra Shallow Junctions ◽  
Laser Thermal Processing

AbstractLaser Thermal Processing (LTP) involves laser melting of an implantation induced preamorphized layer to form highly doped ultra shallow junctions in silicon. In theory, a large number of interstitials remain in the end of range (EOR) just below the laser-formed junction. There is also the possibility of quenching in point defects during the liquid phase epitaxial regrowth of the melt region. Since post processing anneals are inevitable, it is necessary to understand both the behavior of these interstitials and the nature of point defects in the recrystallized-melt region since they can directly affect deactivation and enhanced diffusion. In this study, an amorphizing 15 keV 1 x 1015/cm2 Si+ implant was done followed by a 1 keV 1 x 1014/cm2 B+ implant. The surface was then laser melted at energy densities between 0.74 and 0.9 J/cm2 using a 308 nm excimer-laser. It was found that laser energy densities above 0.81 J/cm2 melted past the amorphous-crystalline interface. Post-LTP furnace anneals were performed at 750°C for 2 and 4 hours. Transmission electron microscopy was used to analyze the defect formation after LTP and following furnace anneals. Secondary ion mass spectrometry measured the initial and final boron profiles. It was observed that increasing the laser energy density led to increased dislocation loop formation and increased diffusion after the furnace anneal. A maximum loop density and diffusion was observed at the end of the process window, suggesting a correlation between the crystallization defects and the interstitial evolution.

Transient And Spatial Radiative Properties Of Patterned Wafers During Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
Peter Y. Wong ◽  
Ioannis N. Miaoulis ◽  
Cynthia G. Madras
Keyword(s):  
Heat Transfer ◽  
Heat Source ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Temporal Variations ◽  
Radiative Properties ◽  
Wafer Surface ◽  
Patterned Wafers ◽  
Thermal Radiative Properties ◽  
Dynamic Variations

AbstractTemperature measurements and processing uniformity continue to be major issues in Rapid Thermal Processing. Spatial and temporal variations in thermal radiative properties of the wafer surface are sources of non-uniformities and dynamic variations. These effects are due to changes in spectral distribution (wafer or heat source), oxidation, epitaxy, silicidation, and other microstructural transformations. Additionally, other variations are induced by the underlying (before processing) and developing (during processing) patterns on the wafer. Numerical simulations of Co silicidation that account for these factors are conducted to determine the radiative properties, heat transfer dynamics, and resultant processing uniformity.

Ripple Technique; a Novel Non-Contact Wafer Emissivity and Temperature Method for RTP

1991 ◽  
Vol 224 ◽  
Author(s):  
C. Schietinger ◽  
B. Adams ◽  
C. Yarling
Keyword(s):  
Optical Fiber ◽  
Measurement Technique ◽  
Thermal Processing ◽  
High Speed ◽  
Rapid Thermal Processing ◽  
Wafer Surface ◽  
Speed Measurement ◽  
Temperature Method ◽  
Emissivity Measurement ◽  
Emissivity Measurements

AbstractA novel wafer temperature and emissivity measurement technique for rapid thermal processing (RTP) is presented. The ‘Ripple Technique’ takes advantage of heating lamp AC ripple as the signature of the reflected component of the radiation from the wafer surface. This application of Optical Fiber Thermometry (OFT) allows high speed measurement of wafer surface temperatures and emissivities. This ‘Ripple Technique’ is discussed in theoretical and practical terms with wafer data presented. Results of both temperature and emissivity measurements are presented for RTP conditions with bare silicon wafers and filmed wafers.

Silicon Rapid Thermal Processing with Ripple Pyrometry

1997 ◽  
Vol 502 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Wide Field ◽  
Loop Control ◽  
Dopant Activation ◽  
Integrated Circuit Fabrication ◽  
Metal Silicides ◽  
Circuit Fabrication ◽  
Infrared Lamps

ABSTRACTThermal processing in silicon integrated circuit fabrication steps for dopant activation, metal silicides, annealing, and oxidation commonly uses single-wafer furnaces that rapidly heat wafers with incandescent infrared lamps. Radiation pyrometers and thermocouple probes are the principle methods of measuring wafer temperature for closed-loop control of rapid thermal processes. The challenge with thermocouples is in dealing with heat from the lamps and non-ideal thermally resistive wafer contact. The challenge with pyrometry is in compensating for the variable emissivity of wafer surfaces and suppressing interference from the lamps. Typical deposited or grown layers of silicon nitride, silicon dioxide, and polycrystalline silicon can produce dramatic changes in emissivity. Layer thicknesses and composition are generally not known with sufficient accuracy, so a method for real time in situ emissivity compensation is required. Accufiber introduced a “ripple technique” to address this issue. The idea is to use two probes, separately sensing radiation from the wafer and the lamps, and extracting AC and quasi-DC parts from each. The AC signals provide a measure of the reflectivity of the wafer, and thence emissivity, as well as the fraction of reflected lamp radiation present in the DC signals. Lucent Technologies introduced a method of using AC lamp ripple to measure wafer temperatures with two radiation probes at a wall in the furnace. One probe views radiation emanating from the wafer through a gap in the lamp array. The other probe has a wide field of view to include lamp radiation. The accuracy of Lucent devices, determined from process results on wafers with various emissivities, is typically in the range of 12°C to 18°C at three standard deviations.

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