Nickel Silicide Work Function Tuning Study In Metal-Gate CMOS Applications

2004 ◽  
Vol 829 ◽  
Author(s):  
Jun Yuan ◽  
Grant Z. Pan ◽  
Yu-Lin Chao ◽  
Jason C.S. Woo
Keyword(s):  
Work Function ◽  
High Performance ◽  
Gate Oxide ◽  
Nickel Silicide ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Oxide Interface ◽  
Metal Gate ◽  
Activation Temperature ◽  
Pile Up

ABSTRACTMid-gap work function (∼4.7eV) for mono-nickel-silicide (NiSi) was obtained by extrapolating flat band voltages of metal-oxide-semiconductor (MOS) capacitors with different gate oxide thickness. Both silicidation temperature and time can affect the nickel silicide work function as a result of different Ni:Si ratio close to the gate oxide interface. Arsenic implantation into the polysilicon before silicidation can shift the NiSi work function towards the silicon conduction band, which makes it suitable for high performance NMOS applications. The physical mechanism responsible for this work function shift is arsenic pile-up at the oxide interface during the nickel silicidation process. Therefore, dual work function metal gate can be obtained by using a single gate full silicidation process. Silicidation temperature and time also affect the work function shift from arsenic dopant, and the incomplete gate silicidation can have the maximum work function modification effect. Arsenic activation temperature before silicidation was found to have a significant effect on the work function shift. Un-annealed samples exhibit a minimum shift in work function due to the low dopant pile-up concentration at the oxide interface.

Study of metal gate work function modulation using plasma and SiH4 treated TiN thin films

2003 ◽  
Vol 786 ◽  
Author(s):  
F. Fillot ◽  
S. Maîtrejean ◽  
T. Farjot ◽  
B. Guillaumot ◽  
B. Chenevier ◽  
...  
Keyword(s):  
Thin Films ◽  
Work Function ◽  
Film Growth ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Flat Band ◽  
Metal Gate ◽  
Polysilicon Gate ◽  
Tin Thin Films ◽  
Tin Metal

ABSTRACTAs gate oxide thickness decreases, the capacitance associated with the depleted layer in polysilicon gate becomes significant, making it necessary to consider alternative gate electrodes. Titanium nitride (TiN) films elaborated with TiCl4 precursor is widely studied as metal gate in semi-conductor technology. In this work, a study of TiN metal gate deposited by MOCVD using TDMAT (Tetrakisdimethylamino titanium) precursor is proposed. N2, H2 plasma application and SiH4 treatment after TiN thin film growth modify composition and microstructure. Consequently, they alter the physical properties of films. Such treatments may be a way to modulate work function and thus to control threshold voltage.Metallic layers were deposited in a chamber using a commercial 8 inch wafer deposition tool. In this study, structural and compositional properties of TiN were correlated with work function measurements. Firstly, the composition evolution (carbon content) was studied by AES and SIMS as a function of plasma and SiH4 treatments; XRD gave details on the microstructure. Secondly, MOS structures were processed on uniformly p-type doped wafers. C-V curves of capacitors were used to estimate the flat band voltage (VFB) and gave access to the work function, the effect of oxide fixed charges and the density of interface states. It is shown that as-deposited amorphous films exhibit a work function of 4.4 eV. Exposure to SiH4 is shown to increase this work function of about 150 meV. Thin films properties are not impacted by anneal treatments. Work function stability was tested at 425 °C, 900 °C and 1050 °C. Thermodynamic compatibility with gate oxide was verified thanks to experimental results and calculations.

Stacked Metal Layers as Gates for MOSFET Threshold Voltage Control

2003 ◽  
Vol 765 ◽  
Author(s):  
Wei Gao ◽  
John F. Conley ◽  
Yoshi Ono Sharp
Keyword(s):  
Metal Oxide ◽  
Work Function ◽  
Threshold Voltage ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Metal Layer ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Metal Gate

AbstractTwo layer metal gate stacks allow the effective work function to be tuned by varying the thickness of the first metal layer. Metal-oxide-semiconductor (MOS) capacitors were fabricated by using two metals of very different work functions on thermal oxide gate dielectric where the bottom layer thickness is varied over a range from 0 to 50nm. Electrical and thermal stability measurements were performed on the Al on TaN metal gate stack. The effective workfunction is seen to shift from the value of one metal to the other rapidly as the thickness of the first metal layer is varied from 0 to approximately 10nm. The flat band voltage (Vfb) transition matches the workfunction difference of the two metals in the stack. The advantage of this approach when applied to metal-oxide-semiconductor-field-effect-transistors (MOSFETs) is that it allows the effective workfunction of the metal stack, and the threshold voltage (Vth) of the device to be fine tuned. It also allows for eventual dual gate complementary MOS (CMOS) device fabrication where two different work function metal stacks are necessary, without processing directly on the gate dielectric. A model is proposed to elucidate the workfunction tuning mechanism.

scholarly journals Comparative Study ofSiO2,Al2O3, and BeO Ultrathin Interfacial Barrier Layers in Si Metal-Oxide-Semiconductor Devices

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
J. H. Yum ◽  
J. Oh ◽  
Todd. W. Hudnall ◽  
C. W. Bielawski ◽  
G. Bersuker ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Performance ◽  
Field Effect Transistors ◽  
Beryllium Oxide ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Effective Electron

In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.

scholarly journals Performance Measures of Different Gate Oxide Materials in Gate All Around Fet

2020 ◽  
Vol 9 (2) ◽  
pp. 23-25
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Oxide Semiconductor ◽  
Oxide Materials ◽  
Performance Limits ◽  
Short Channel ◽  
Advanced Technique ◽  
And Performance

The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipated technique for developing nanowire structures. By considering these issues, in this paper, we developed a simulation model that provides accurate results basing on Gate layout and multi-gate NW FET's so that the scaling can be increased few nanometers long and performance limits gradually increases. The model developed is SILVACO that tests the action of FET with different gate oxide materials.

scholarly journals Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications

2020 ◽  
Vol 10 (7) ◽  
pp. 2499 ◽  
Author(s):  
Namrata Mendiratta ◽  
Suman Lata Tripathi ◽  
Sanjeevikumar Padmanaban ◽  
Eklas Hossain
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Biomedical Applications ◽  
Field Effect Transistor ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Interface ◽  
Heavily Doped ◽  
Effect Transistor

The Complementary Metal-Oxide Semiconductor (CMOS) technology has evolved to a great extent and is being used for different applications like environmental, biomedical, radiofrequency and switching, etc. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based biosensors are used for detecting various enzymes, molecules, pathogens and antigens efficiently with a less time-consuming process involved in comparison to other options. Early-stage detection of disease is easily possible using Field-Effect Transistor (FET) based biosensors. In this paper, a steep subthreshold heavily doped n+ pocket asymmetrical junctionless MOSFET is designed for biomedical applications by introducing a nanogap cavity region at the gate-oxide interface. The nanogap cavity region is introduced in such a manner that it is sensitive to variation in biomolecules present in the cavity region. The analysis is based on dielectric modulation or changes due to variation in the bio-molecules present in the environment or the human body. The analysis of proposed asymmetrical junctionless MOSFET with nanogap cavity region is carried out with different dielectric materials and variations in cavity length and height inside the gate–oxide interface. Further, this device also showed significant variation for changes in different introduced charged particles or region materials, as simulated through a 2D visual Technology Computer-Aided Design (TCAD) device simulator.

Ultralow work function of scandium metal gate with tantalum nitride interface layer for n-channel metal oxide semiconductor application

2007 ◽  
Vol 90 (10) ◽  
pp. 103510 ◽  
Author(s):  
Musarrat Hasan ◽  
Hokyung Park ◽  
Hyundoek Yang ◽  
Hyunsang Hwang ◽  
Hyung-Suk Jung ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Work Function ◽  
Interface Layer ◽  
Metal Oxide Semiconductor ◽  
Tantalum Nitride ◽  
Oxide Semiconductor ◽  
Metal Gate

scholarly journals Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

2021 ◽  
Author(s):  
Suraj Cheema ◽  
Nirmaan Shanker ◽  
Li-Chen Wang ◽  
Cheng-Hsiang Hsu ◽  
Shang-Lin Hsu ◽  
...  
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Atomic Scale ◽  
Oxide Semiconductor ◽  
Operating Voltage ◽  
Gate Stacks ◽  
Gate Stack ◽  
Gate Oxide Thickness

Abstract With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

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