scholarly journals Logic-level Evidence Retrieval and Graph-based Verification Network for Table-based Fact Verification

2021 ◽  
Author(s):  
Qi Shi ◽  
Yu Zhang ◽  
Qingyu Yin ◽  
Ting Liu
Keyword(s):  
Logic Level

Logic Level Modeling

1995 ◽  
pp. 87-126
Author(s):  
Donald E. Thomas ◽  
Philip R. Moorby
Keyword(s):  
Logic Level

Low Power Arithmetic Circuit Design for Multimedia Applications

2016 ◽  
pp. 252-282
Author(s):  
Senthil C. Pari
Keyword(s):  
Low Power ◽  
High Performance ◽  
Design Method ◽  
Propagation Delay ◽  
Arithmetic Circuit ◽  
Noise Margin ◽  
Binary Arithmetic ◽  
Pass Transistor ◽  
Circuit Family ◽  
Logic Level

The objective of this chapter is to describe the various designed arithmetic circuit for an application of multimedia circuit that can be used in a high-performance or mobile microprocessor with a particular set of optimisation criteria. The aim of this chapter is to describe the design method of binary arithmetic especially using by CMOS and Pass Transistor Logic technique. The pass transistor techniques are reduced the noise margin for small circuit, which can be explained in this chapter. This chapter further describe the types of arithmetic and its techniques. The technique design principle procedure should make the following decisions: circuit family (complementary static CMOS, pass-transistor, or Shannon Theorem based); type of arithmetic to be used. The decisions on the designed logic level significantly affect the propagation delay, area and power dissipation.

High-Performance SIP Half-Bridge IPM Based on 35mΩ/1200V SiC Stack-Cascode

2020 ◽  
Vol 1004 ◽  
pp. 1016-1021
Author(s):  
Peter Alexandrov ◽  
Anup Bhalla ◽  
Xue Qing Li ◽  
Jens Eltze
Keyword(s):  
High Performance ◽  
Control Voltage ◽  
Switching Losses ◽  
High Side ◽  
Power Modules ◽  
Logic Level ◽  
Gate Charge

A SiC-based high-performance Intelligent Power Modules (IPM) was developed. It is a System In Package (SIP) module that consist of a half-bridge with driver. In the developed SIP IPM, the internal half-bridge is made up of UnitedSiC 35mΩ/1200V Stack-Cascode switches (UF3SC120035Z) which have low on-resistance, low gate charge, simple gate drive of VGS=0 or-5V to VGS=12V, excellent integral body diode and very low switching losses. The module operates with control voltage of 12-15V for both the low and high side switches, and a logic level input that can be 3.3V, 5V or 12V. We believe that this module will enable extremely efficient switching up to 250-400kHz, depending on topology, offering several hundred kHz even in hard-switched applications.

1990 Workshop on Logic Level Modeling for ASICs final report

1991 ◽  
Vol 21 (1) ◽  
pp. 56-69
Author(s):  
Mark Glasser ◽  
Rob Mathews ◽  
John M. Acken
Keyword(s):  
Final Report ◽  
Logic Level

scholarly journals Monolithic Integrated High Frequency GaN DC-DC Buck Converters with High Power Density Controlled by Current Mode Logic Level Signal

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1540
Author(s):  
Longkun Lai ◽  
Ronghua Zhang ◽  
Kui Cheng ◽  
Zhiying Xia ◽  
Chun Wei ◽  
...  
Keyword(s):  
Power Density ◽  
Current Mode ◽  
Buck Converter ◽  
Switching Frequency ◽  
High Power Density ◽  
Current Mode Logic ◽  
Power Stage ◽  
Amplifier Stage ◽  
Gate Driver ◽  
Logic Level

Integration is a key way to improve the switching frequency and power density for a DC-DC converter. A monolithic integrated GaN based DC-DC buck converter is realized by using a gate driver and a half-bridge power stage. The gate driver is composed of three stages (amplitude amplifier stage, level shifting stage and resistive-load amplifier stage) to amplify and modulate the driver control signal, i.e., CML (current mode logic) level of which the swing is from 1.1 to 1.8 V meaning that there is no need for an additional buffer or preamplifier for the control signal. The gate driver can provide sufficient driving capability for the power stage and improve the power density efficiently. The proposed GaN based DC-DC buck converter is implemented in the 0.25 μm depletion mode GaN-on-SiC process with a chip area of 1.7 mm × 1.3 mm, which is capable of operating at high switching frequency up to 200 MHz and possesses high power density up to 1 W/mm2 at 15 V output voltage. To the authors’ knowledge, this is the highest power density for GaN based DC-DC converter at the hundreds of megahertz range.

Accurate Logic-Level Current Estimation for Digital CMOS Circuits

2006 ◽  
Vol 2 (1) ◽  
pp. 87-94
Author(s):  
P. Ruiz-de-Clavijo ◽  
J. Juan-Chico ◽  
M. J. Bellido ◽  
A. Millán ◽  
D. Guerrero ◽  
...  
Keyword(s):  
Cmos Circuits ◽  
Digital Cmos ◽  
Current Estimation ◽  
Logic Level
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