scholarly journals Mixed baseband architecture based on FBD ΣΔ–based ADC for multistandard receivers

ACTA IMEKO ◽  
2015 ◽  
Vol 4 (3) ◽  
pp. 14
Author(s):  
Rihab Lahouli ◽  
Manel Ben-Romdhane ◽  
Chiheb Rebai ◽  
Dominique Dallet
Keyword(s):  
Software Defined Radio ◽  
Hardware Implementation ◽  
Dynamic Range ◽  
Filter Design ◽  
Automatic Gain Control ◽  
System Level ◽  
Sigma Delta ◽  
Matlab Simulink ◽  
Digital Reconstruction ◽  
Multistandard Receiver

<p>This paper presents the design and simulation results of a novel mixed baseband stage for a frequency band decomposition (FBD) analog-to-digital converter (ADC) in a multistandard receiver. The proposed FBD-based ADC architecture is flexible with programmable parallel branches composed of discrete time (DT) 4<sup>th</sup> order single-bit Sigma-Delta modulators. The mixed baseband architecture uses a single non-programmable anti-aliasing filter (AAF) avoiding the use of an automatic gain control (AGC) circuit. System level analysis proved that the proposed FBD architecture satisfies design specifications of the software defined radio (SDR) receiver. In this paper, the authors focus on the Butterworth AAF filter design for a multistandard receiver. Besides, theoretical analysis of the reconstruction stage for UMTS test case is discussed. It leads to a complicated system of equations and high digital filter orders. To reduce the digital reconstruction stage complexity, the authors propose an optimized digital reconstruction stage architecture design. The demodulation-based digital reconstruction stage using two decimation stages has been implemented using MATLAB/SIMULINK. Technical choices and performances are discussed. The computed signal-to-noise ratio (SNR) of the MATLAB/SIMULINK FBD ADC model is equal to at least 75 dB which satisfies the dynamic range required for UMTS signals. Next to hardware implementation with quantized filters coefficients, the authors implemented their proposition in VHDL in a SysGen environment. The measured SNR of the hardware implementation is equal to 74.08 dB which satisfies the required dynamic range of UMTS signals.</p>

scholarly journals Optimized System Level Hardware Realization of Built-in-Self-Test Approach for Sigma-Delta Analog-to-Digital Converter

2016 ◽  
Vol 4 (3) ◽  
pp. 85-90
Author(s):  
Anil Kumar Sahu ◽  
Vivek Kumar Chandra ◽  
G R Sinha
Keyword(s):  
System Level ◽  
Dynamic Parameters ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Matlab Simulink ◽  
Analog To Digital ◽  
System Level Modeling ◽  
Self Test ◽  
Sigma Delta Adc

System-level modeling is generally needed due to simultaneous increase in design complexity with multi-million gate designs in today’s system-on-chips (SoCs). System C is generally applied to system-level modeling of Sigma-Delta ADC. CORDIC technique and test generation for the testing of mixed signal circuit components such as analog-to-digital converter is mostly implemented in system level modeling. This work focuses on developing fast and yet accurate model of BIST approach for Sigma-Delta ADC. The Sigma-Delta modulator’s ADC static parameters as well as dynamic parameters are degraded. One of the dynamic parameters, signal-to-noise ratio (SNR) is directly obtained by the SIMSIDES (MATLAB SIMULINK tool). Then, the obtained parameters are tested by using Built-in-self-test that is desirable for the VLSI system in order to reduce the non-recurring cost (NRE) per chip by the manufacturer. This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK and Xilinx EDA tool environment. This work also contributes towards the Output Response Analyzer (ORA) being used for testing parameters which help in reducing the difficulties in design of the complete ORA circuit. Moreover, the reusable features of hardware in the computation of different parameters are also improved in the ORA design.

An Optimized Design Strategy for the Hardware Implementation of the Hearing Aid Algorithms

2015 ◽  
Vol 719-720 ◽  
pp. 548-553
Author(s):  
Feng Guo ◽  
Shan Shan Yong ◽  
Zhao Yang Guo ◽  
Xin An Wang ◽  
Guo Xin Zhang
Keyword(s):  
Hardware Implementation ◽  
Dynamic Range ◽  
Automatic Gain Control ◽  
Hearing Aid ◽  
Gain Control ◽  
Design Strategy ◽  
Optimized Design ◽  
Wide Dynamic Range ◽  
Dynamic Range Compression ◽  
The Common

In this paper, a new design strategy for the hardware implementation of hearing aid algorithms is proposed. Two familiar hearing aid algorithms—Wide Dynamic Range Compression (WDRC) and Automatic Gain Control (AGC)—are implemented in one circuit as an example. By putting the common arithmetic procedures into common module, the operation units can be used repeatedly. In this way, the area and power consumption are visibly reduced.

scholarly journals PROGRAMMABLE PARALLEL FBD SIGMA DELTA ADC RECONSTRUCTION STAGE DESIGN FOR SOFTWARE DEFINED RADIO RECEIVER

2016 ◽  
pp. 14-21
Author(s):  
Rihab Lahouli ◽  
Manel Ben-Romdhane ◽  
Chiheb Rebai ◽  
Dominique Dallet
Keyword(s):  
Software Defined Radio ◽  
Signal To Noise Ratio ◽  
Parallel Architecture ◽  
Use Case ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Modulators ◽  
Digital Reconstruction ◽  
Simulation Results ◽  
Sigma Delta Adc

Today’s bottleneck of signal processing in multistandard software defined radio (SDR) receiver is the analog-to-digital converter (ADC). Therefore, the authors present in this paper the design and simulation results of a programmable parallel frequency band decomposition (FBD) architecture for ADC. The designed parallel architecture is composed of six parallel branches based on discrete-time (DT) 4th order sigma delta modulators using single-bit quantizers. Each branch processes a sub-bandwidth of the received signal. Only needed branches are selected according to the chosen standard. The parallel sigma delta modulators’ outputs are handled by a demodulation-based digital reconstruction stage in order to provide the FBD sigma delta-based ADC output signal. The digital reconstruction stage differs from one communication standard to another. In this paper, its design is discussed for the UMTS use case. The objective is to propose a digital reconstruction design with optimized complexity. In fact, the authors propose a comparative study between some configurations of demodulation, decimation and filtering processes. Technical choices and simulation results are discussed. For UMTS use case, the proposed FBD sigma delta-based ADC architecture ensures a computed signal-to-noise ratio (SNR) over 74 dB.

System-Level Mitigation of Undersampling ADC Nonlinearity for High-IF Radio Receivers

Frequenz ◽  
2012 ◽  
Vol 66 (9-10) ◽  
Author(s):  
Georg Vallant ◽  
Michael Epp ◽  
Markus Allén ◽  
Mikko Valkama ◽  
Friedrich K. Jondral
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
Dynamic Range ◽  
System Level ◽  
General Validity ◽  
Radio Receivers ◽  
Rf Signals ◽  
Spurious Free Dynamic Range ◽  
Digital Linearization ◽  
Free Dynamic

AbstractOver the last years ongoing advances in ADC technology have enabled RF signals to be sampled at IF frequencies. Undersampling is nowadays employed in software-defined radio or radar receivers and offers the possibility to relieve requirements in the analog receiver partition. Unfortunately, when moving to higher IF concepts, this becomes demanding for the ADC itself, because of inherent spurious-free dynamic range (SFDR) roll-off that increases with input frequency. This fact often limits the receiver's IF placement to Nyquist zone (NZ) 2. In this work the emerging concept of Digital Assistance is pursued to give the receiver access to higher NZs while making no compromise on the SFDR. We will present and discuss post-correction results for two 16-bit high-speed converters from two different vendors at 120 and 125 MSPS, respectively. The proposed system-level post-correction decomposes nonlinearity into a static and a dynamic part. For both ADCs under investigation the degraded SFDR in higher NZs could be improved by up to 15 dB using purely digital linearization technologies, thus increasing the detectability of small signals in the presence of very strong signals or interferers. Near-identical results for both ADCs confirm the general validity of the system-level correction approach.

A Low-Distortion Fourth-Order Bandpass Sigma-Delta Modulator Using Double-Sampling Technique

2013 ◽  
Vol 562-565 ◽  
pp. 1058-1062 ◽  
Author(s):  
Hong Lin Xu ◽  
Jia Jun Zhou ◽  
Jian Yang ◽  
Song Chen ◽  
Zhi Qiang Gao ◽  
...  
Keyword(s):  
Fourth Order ◽  
Dynamic Range ◽  
Sampling Technique ◽  
System Level ◽  
Double Sampling ◽  
Cmos Process ◽  
Sigma Delta ◽  
System Level Simulation ◽  
Low Distortion ◽  
Σδ Modulator

In this paper, a low-distortion fourth-order bandpass sigma-delta (ΣΔ) modulator is proposed based on a switched-capacitor resonator which employs double-sampling technique to relax the requirements for circuits and reduce opamp power consumption and chip area. The modulator is based on the low-distortion low pass ΣΔ modulator. The system level simulation results compare between the low-distortion architecture and the traditional one is given. The full differential circuit applying two-path technique is implemented with TSMC0.18µm CMOS process. It achieves a peak SNR (signal-to-noise ratio) of 85.9dB and DR (dynamic range) of 91dB with 200 kHz bandwidth centered at 20MHz which are better than the conventional bandpass ΣΔ modulator.

Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 723-727
Author(s):  
Wen Jie Fan ◽  
Qiu Ye Lv ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
Architectural Design ◽  
Simple Structure ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Sigma Delta Adc

Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

scholarly journals EMC Component Modeling and System-Level Simulations of Power Converters: AC Motor Drives

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1568
Author(s):  
Bernhard Wunsch ◽  
Stanislav Skibin ◽  
Ville Forsström ◽  
Ivica Stevanovic
Keyword(s):  
Power Converters ◽  
Filter Design ◽  
Magnetic Coupling ◽  
Power Converter ◽  
System Level ◽  
Noise Propagation ◽  
Ac Motor ◽  
Input Side ◽  
Indispensable Tool ◽  
Set Up

EMC simulations are an indispensable tool to analyze EMC noise propagation in power converters and to assess the best filtering options. In this paper, we first show how to set up EMC simulations of power converters and then we demonstrate their use on the example of an industrial AC motor drive. Broadband models of key power converter components are reviewed and combined into a circuit model of the complete power converter setup enabling detailed EMC analysis. The approach is demonstrated by analyzing the conducted noise emissions of a 75 kW power converter driving a 45 kW motor. Based on the simulations, the critical impedances, the dominant noise propagation, and the most efficient filter component and location within the system are identified. For the analyzed system, maxima of EMC noise are caused by resonances of the long motor cable and can be accurately predicted as functions of type, length, and layout of the motor cable. The common-mode noise at the LISN is shown to have a dominant contribution caused by magnetic coupling between the noisy motor side and the AC input side of the drive. All the predictions are validated by measurements and highlight the benefit of simulation-based EMC analysis and filter design.

High Dynamic Range (HDR) Signal Processing on Software-Defined Radio

2020 ◽  
Author(s):  
Phillip V. Do ◽  
Jesse Hernandez ◽  
Zhao Lu ◽  
Danson Evan Garcia ◽  
Steve Mann
Keyword(s):  
Signal Processing ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
High Dynamic

scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

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