scholarly journals Novel Hybrid SETMOS Logic for Ultra-low-power Applications

2021 ◽  
Author(s):  
Raj Sanjivkumar Shah ◽  
Rutu Parekh ◽  
Rasika Dhavse
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Room Temperature ◽  
Logic Gates ◽  
Logic Circuits ◽  
Total Power ◽  
Ultra Low Power ◽  
Temperature Variations ◽  
Electron Transistors

Abstract This paper investigates the Single-GateSingle Electron Transistors (SG-SETs) based hybrid SETMOS logic circuits for ultra-low-power applications at room temperature. The methodological design of the proposed hybrid SETMOS logic circuits is compatible with 22- nm CMOS bias and process. The widely acclaimed Mahapatra-IonescuBannerjee (MIB) model is modified to implement the proposed SG-SET and hybrid SETMOS logic circuits using Verilog-A. Logic inverter, two-input NAND, NOR, AND, OR, EX-OR, and EX-NOR logic gates are simulated at room temperature using novel SETMOS hybridization. The proposed work is compared with the 22-nm CMOS counterpart (simulated with the same setup). We found that the reduction in total power dissipation by 98.04%, 96.45%, 94.65%, 93.7%, 92.63%, 93.52%, 95.57% using hybrid SETMOS NAND, NOR, AND, EX-OR and EXOR gates than 22 nm CMOS logic gates. The proposed work is compared with other works of literature. We also examined the robustness of the proposed logic circuits against temperature variations from 77 K to 500 K.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

scholarly journals Adiabatic superconducting cells for ultra-low-power artificial neural networks

2016 ◽  
Vol 7 ◽  
pp. 1397-1403 ◽  
Author(s):  
Andrey E Schegolev ◽  
Nikolay V Klenov ◽  
Igor I Soloviev ◽  
Maxim V Tereshonok
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Artificial Neural Networks ◽  
Low Power ◽  
Power Dissipation ◽  
Radial Basis Function Networks ◽  
Activation Functions ◽  
Ultra Low Power ◽  
Network Algorithms ◽  
Low Power Dissipation

We propose the concept of using superconducting quantum interferometers for the implementation of neural network algorithms with extremely low power dissipation. These adiabatic elements are Josephson cells with sigmoid- and Gaussian-like activation functions. We optimize their parameters for application in three-layer perceptron and radial basis function networks.

InAs/AlSb HEMTs for cryogenic LNAs at ultra-low power dissipation

2011 ◽  
Vol 64 (1) ◽  
pp. 47-53 ◽  
Author(s):  
Giuseppe Moschetti ◽  
Niklas Wadefalk ◽  
Per-Åke Nilsson ◽  
Yannick Roelens ◽  
Albert Noudeviwa ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Ultra Low Power ◽  
Low Power Dissipation
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