scholarly journals Junctionless Gate-All-Around Nanowire FET with Asymmetric Spacer for Continued Scaling

2021 ◽  
Author(s):  
Bharath Sreenivasulu Vakkalak ◽  
Vadthiya Narendar
Keyword(s):  
Electrical Properties ◽  
Cutoff Frequency ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Gate Length ◽  
Dynamic Power ◽  
Gate Capacitance ◽  
Static Power ◽  
Rf Applications

Abstract In this paper we have performed scaling performance of asymmetric junctionless (JL) SOI nanowire FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are performed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = 64 mV/dec, drain induced barrier lowering (DIBL) = 45 mV/V, and switching ratio (ION/IOFF) = 106 shows a higher level of electrostatic integrity. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (I), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are determined. Furthermore, the dynamic power (DP) and static power (SP) consumption of the device with scaling is also presented. The findings of the study show that asymmetric JL nanowire FET is one of the scaling possibilities.

scholarly journals Scaling Behavior of Sub-100 nm InAlN/GaN HEMTs on Silicon for RF Applications

2021 ◽  
Author(s):  
Peng Cui ◽  
Yuping Zeng
Keyword(s):  
Cutoff Frequency ◽  
Equivalent Circuit Model ◽  
Scaling Behavior ◽  
Gate Length ◽  
High Electron ◽  
Intrinsic Parameters ◽  
Gan Hemt ◽  
Gan Hemts ◽  
Rf Applications ◽  
20 Nm

Abstract Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg­ scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

scholarly journals Scaling Behavior of InAlN/GaN HEMTs on Silicon for RF Applications

2022 ◽  
Author(s):  
Peng Cui ◽  
Yuping Zeng
Keyword(s):  
Cutoff Frequency ◽  
Equivalent Circuit Model ◽  
Scaling Behavior ◽  
Gate Length ◽  
High Electron ◽  
Intrinsic Parameters ◽  
Gan Hemt ◽  
Gan Hemts ◽  
Rf Applications ◽  
20 Nm

Abstract Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg­ scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

scholarly journals An Investigation of the Physical and Electrical Properties of Knitted Electrodes When Subjected to Multi-Axial Compression and Abrasion

Proceedings ◽  
2021 ◽  
Vol 68 (1) ◽  
pp. 2
Author(s):  
Arash M. Shahidi ◽  
Theodore Hughes-Riley ◽  
Carlos Oliveira ◽  
Tilak Dias
Keyword(s):  
Heart Rate ◽  
Electrical Properties ◽  
Applied Load ◽  
Pressure Sensors ◽  
Electrical Performance ◽  
Electronic Textiles ◽  
Heart Rate Monitors ◽  
Mechanical Loads ◽  
And Performance ◽  
Over Time

Knitted electrodes are a key component to many electronic textiles including sensing devices, such as pressure sensors and heart rate monitors; therefore, it is essential to assess the electrical performance of these knitted electrodes under different mechanical loads to understand their performance during use. The electrical properties of the electrodes could change while deforming, due to an applied load, which could occur in the uniaxial direction (while stretched) or multiaxial direction (while compressed). The properties and performance of the electrodes could also change over time when rubbed against another surface due to the frictional force and generated heat. This work investigates the behavior of a knitted electrode under different loading conditions and after multiple abrasion cycles.

1510 mS/mm 0.1 [micro sign]m gate length pseudomorphic HEMTs with intrinsic current gain cutoff frequency of 220 GHz

1996 ◽  
Vol 32 (9) ◽  
pp. 848 ◽  
Author(s):  
F. Diette ◽  
D. Langrez ◽  
J.L. Codron ◽  
E. Delos ◽  
D. Theron ◽  
...  
Keyword(s):  
Cutoff Frequency ◽  
Current Gain ◽  
Gate Length

Optimum Design of Inductors Used for Wireless Power Transmission Micro-Module

2004 ◽  
Author(s):  
Chao-Liang Chang ◽  
Uei-Ming Jow ◽  
Chao-Ta Huang ◽  
Hsiang-Chi Liu ◽  
Jr-Yuan Jeng ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Electrical Properties ◽  
Optimum Design ◽  
Thermal Loading ◽  
Power Transmission ◽  
Thermal Strain ◽  
Electrical Performance ◽  
Wireless Power ◽  
Wireless Power Transmission ◽  
Analysis Software

The micro-inductor is a key component in wireless power transmission micro modules. In this paper, an optimum design for the micro-inductor was studied and related MEMS fabrication techniques were also developed. Commercial electromagnetic property analysis software, ANSOFT, was used to screen the main design factors of the micro-inductor. It was found that the high inductance and high quality factors of the micro-inductor implied high power transmission efficiency for the micro-module’s wireless power transmission. The electrical performance of the micro-inductor was affected by the thermal stress and thermal strain induced in the operational environment of the wireless power transmission micro-module. In order to investigate the reliability of the micro-inductor, commercial stress analysis software, ANSYS, was used to calculate thermal stress and thermal strain. The deformed model of the micro-inductor was then imported into ANSOFT in order to calculate its electrical properties. Glass substrate Pyrex 7740 was used to reduce the substrate loss of the magnetic flux of the micro-inductor. The surface micromachining technique, a kind of MEMS processing, was chosen to fabricate the micro-inductor; the coil of the micro-inductor was electroplated with copper to reduce the series resistance. The minimum line width and line space of the coil were 20 μm and 20 μm respectively. Polyimide (PI) was used for supporting the structure of micro-inductors. The maximum shear stress was 74.09MPa and the maximum warpage was 2.197 μm at a thermal loading of 125°C. For the simulated data, the most suitable areas for 31-turn and 48-turn coils were at an area ratio of 1.27 and 2, respectively. The electrical properties of the inductors changed slightly under thermal loading.

Strain-engineering in AlGaN/GaN HEMTs: impact of silicon nitride passivation layer on electrical performance

2021 ◽  
Author(s):  
Sanghamitra Das ◽  
Taraprasanna Dash ◽  
Devika Jena ◽  
Eleena Mohapatra ◽  
C K Maiti
Keyword(s):  
Experimental Data ◽  
Compressive Strain ◽  
Cutoff Frequency ◽  
Strain Engineering ◽  
Electrical Performance ◽  
Current Gain ◽  
Great Promise ◽  
High Electron ◽  
Wide Range ◽  
Gan Hemts

Abstract In this work, we present a physics-based analysis of two-dimensional electron gas (2DEG) sheet carrier density and other microwave characteristics such as transconductance and cutoff frequency of AlxGa1-xN/GaN high electron mobility transistors (HEMT). An accurate polarization-dependent charge control-based analysis is performed for microwave performance assessment in terms of current, transconductance, gate capacitances, and cutoff frequency of lattice-mismatched AlGaN/GaN HEMTs. The influence of stress on spontaneous and piezoelectric polarization is included in the simulation of an AlGaN/GaN HEMT. We have shown the change in threshold voltage (Vt) due to tensile and compressive strain with different gate lengths. Also, the influence of stress due to the change in nitride thickness is presented. Our simulation results for drain current, transconductance, and current-gain cutoff frequency for various gate length devices are calibrated and verified with experimental data over a wide range of gate and drain applied voltages, which are expected to be useful for microwave circuit design. The predicted transconductance, drain conductance, and operation frequency are quite close to the experimental data. The AlGaN/GaN heterostructure HEMTs with nitride passivation layers show great promise as a candidate in future high speed and high power applications.

Ammonius and Philoponus on the Activity of Syllogizing

2021 ◽  
Vol 24 (1) ◽  
pp. 140-160
Author(s):  
Luca Gili
Keyword(s):  
Dynamic Power ◽  
Dynamic Operation ◽  
Static Power

Abstract According to Philoponus, the activity of drawing syllogisms is a dynamic operation. Following the classical idea that actions are specified by their objects and habitual powers by their actions, Philoponus concludes that only a dynamic power can elicit the act of syllogizing. This power is identified with discursive reasoning (dianoia). Imagination, on the contrary, is a static power, that cannot elicit that particular motion of drawing a syllogistic inference. The issue, however, is not entirely uncontroversial, because Ammonius maintains that sophistical syllogisms can only be formed by imagination, since they involve “empty concepts” as terms and only imagination can form such concepts. In this paper I will reconstruct Philoponus’ and Ammonius’ theories about the “activity” of syllogizing, and I shall explain how Philoponus can deal with sophistical syllogisms in a consistent way.

High Layer Count in LTCC Dual Band Antenna for Galileo GNSS

2008 ◽  
Vol 5 (4) ◽  
pp. 156-160 ◽  
Author(s):  
Peter Uhlig ◽  
Dirk Manteuffel ◽  
Stefan Malkmus
Keyword(s):  
Electrical Properties ◽  
Low Temperature ◽  
Patch Antenna ◽  
Process Variations ◽  
Dual Band ◽  
Electrical Performance ◽  
Dual Band Antenna ◽  
Number Of Layers ◽  
High Layer ◽  
Hybrid Coupler

The adaptation of the LTCC (Low Temperature Cofired Ceramics) process for an unusually high number of layers (up to 50) will be described and explained in this paper. Special attention will be paid to lamination, debindering, and cofiring of the LTCC stack. The influence of necessary process variations on electrical properties such as permittivity will be studied. Very often the number of layers is determined by the complexity of the circuit. Here a minimum substrate height is required for the electrical performance of a patch antenna, particularly in terms of bandwidth. A dual band antenna for two Galileo bands at 1.58 GHz and 1.18 GHz was realized as a combination of two coupled patches. Circular polarization was attained by separately feeding each patch with a hybrid coupler. These features add further layers to an already considerable substrate height.

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