Influence of Wire-Bonding Layout on Reliability in IGBT Module

Al wire bonding lift-off is one of the main failure modes of IGBT module. When the severity of the failure mode is different, the temperature character of IGBT is also different. This paper presents a methodology based on 3D electro-thermal coupling finite elements modeling intended to analyze the relation between the failure degree and the temperature, and compares the influence degree of Al wire bonding lift-off to the performance of IGBT module. This method and the corresponding results help to evaluate Al wire bonding lift-off how they influence the performance of IGBT, determine the failure, establish the failure standards and find the optimization of structure design.

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Experimental Demonstration of 1200V IGBT Module for a Magnetic Energy Recovery Switch Application

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.128.677 ◽

2008 ◽

Vol 128 (4) ◽

pp. 677-682 ◽

Cited By ~ 3

Author(s):

Taku Takaku ◽

Noriyuki Iwamuro ◽

Yoshiyuki Uchida ◽

Ryuichi Shimada

Keyword(s):

Energy Recovery ◽

Magnetic Energy ◽

Experimental Demonstration ◽

Igbt Module

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Failure Analysis on Power Trench MOSFET Devices with Copper Wire Bonds

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0223 ◽

2011 ◽

Author(s):

Huixian Wu ◽

Arthur Chiang ◽

David Le ◽

Win Pratchayakun

Keyword(s):

Failure Analysis ◽

Copper Wire ◽

New Technology ◽

Analytical Techniques ◽

Wire Bonding ◽

Bonding Process ◽

Wire Bonds ◽

Copper Wire Bonding ◽

Wet Chemical ◽

Microelectronic Components

Abstract With gold prices steadily going up in recent years, copper wire has gained popularity as a means to reduce cost of manufacturing microelectronic components. Performance tradeoff aside, there is an urgent need to thoroughly study the new technology to allay any fear of reliability compromise. Evaluation and optimization of copper wire bonding process is critical. In this paper, novel failure analysis and analytical techniques are applied to the evaluation of copper wire bonding process. Several FA/analytical techniques and FA procedures will be discussed in detail, including novel laser/chemical/plasma decapsulation, FIB, wet chemical etching, reactive ion etching (RIE), cross-section, CSAM, SEM, EDS, and a combination of these techniques. Two case studies will be given to demonstrate the use of these techniques in copper wire bonded devices.

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Decapsulation Techniques for Cu Wire Bonding Package

ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2009p0217 ◽

2009 ◽

Author(s):

Dongmei Meng ◽

Joe Rupley ◽

Chris McMahon

Keyword(s):

Laser Ablation ◽

Thin Layer ◽

Chemical Etching ◽

Wire Bonding ◽

Methods And Techniques ◽

Wet Chemical ◽

Wet Chemical Etching ◽

Reliability Issue ◽

Etch Time ◽

Device Technology

Abstract This paper presents decapsulation solutions for devices bonded with Cu wire. By removing mold compound to a thin layer using a laser ablation tool, Cu wire bonded packages are decapsulated using wet chemical etching by controlling the etch time and temperature. Further, the paper investigates the possibilities of decapsulating Cu wire bonded devices using full wet chemical etches without the facilitation of laser ablation removing much of mold compound. Additional discussion on reliability concerns when evaluating Cu wirebond devices is addressed here. The lack of understanding of the reliability of Cu wire bonded packages creates a challenge to the FA engineer as they must develop techniques to help understanding the reliability issue associated with Cu wire bonding devices. More research and analysis are ongoing to develop appropriate analysis methods and techniques to support the Cu wire bonding device technology in the lab.

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BGA and Advanced Package Wire to Wire Bonding for Backside Emission Microscopy

ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1999p0365 ◽

1999 ◽

Author(s):

Jim B. Colvin

Keyword(s):

Focused Ion Beam ◽

Ion Beam ◽

Wire Bonding ◽

Preparation Technique ◽

Low Profile ◽

Normal Test ◽

Silicon Thickness ◽

Working Distance ◽

Polished Side ◽

Analytical Tools

Abstract A new method of preparation will be shown which allows traditional fixturing such as test heads and probe stations to be utilized in a normal test mode. No inverted boards cabled to a tester are needed since the die remains in its original package and is polished and rebonded to a new package carrier with the polished side facing upward. A simple pin reassignment is all that is needed to correct the reverse wire sequence after wire to wire bonding or wire to frame bonding in the new package frame. The resulting orientation eliminates many of the problems of backside microscopy since the resulting package orientation is now frontside. The low profile as a result of this technique allows short working distance objectives such as immersion lenses to be used across the die surface. Test equipment can be used in conjunction with analytical tools such as the emission microscope or focused ion beam due to the upright orientation of the polished backside silicon. The relationship between silicon thickness and transmission for various wavelengths of light will be shown. This preparation technique is applicable to advanced packaging methods and has the potential to become part of future assembly processes.

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Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

Applied Sciences ◽

10.3390/app11157057 ◽

2021 ◽

Vol 11 (15) ◽

pp. 7057

Author(s):

Lin Wang ◽

Zhe Cheng ◽

Zhi-Guo Yu ◽

De-Feng Lin ◽

Zhe Liu ◽

...

Keyword(s):

Flip Chip ◽

High Electron Mobility Transistors ◽

Wire Bonding ◽

High Electron ◽

Parasitic Inductance ◽

Switching Performance ◽

Turn On ◽

Electron Mobility Transistors ◽

Chip Technology ◽

Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

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