BGA and Advanced Package Wire to Wire Bonding for Backside Emission Microscopy

Author(s):  
Jim B. Colvin

Abstract A new method of preparation will be shown which allows traditional fixturing such as test heads and probe stations to be utilized in a normal test mode. No inverted boards cabled to a tester are needed since the die remains in its original package and is polished and rebonded to a new package carrier with the polished side facing upward. A simple pin reassignment is all that is needed to correct the reverse wire sequence after wire to wire bonding or wire to frame bonding in the new package frame. The resulting orientation eliminates many of the problems of backside microscopy since the resulting package orientation is now frontside. The low profile as a result of this technique allows short working distance objectives such as immersion lenses to be used across the die surface. Test equipment can be used in conjunction with analytical tools such as the emission microscope or focused ion beam due to the upright orientation of the polished backside silicon. The relationship between silicon thickness and transmission for various wavelengths of light will be shown. This preparation technique is applicable to advanced packaging methods and has the potential to become part of future assembly processes.

Author(s):  
Y. S. Huan ◽  
Y. L. Kuo ◽  
Y.T. Lin ◽  
Jeff Chen ◽  
K.Y. Lee

Abstract Wire bonding is the most highly used interconnection technology in the packaging of integrated circuits. One of the potential risks of wire bonding is the damage on the oxide layers underneath the bond pad. Oxide damage monitoring is necessary to ensure bonding has no impact on the oxide layers under the bond pad. Since the oxide layer is not seen by visual inspection, bond pad stripping is necessary. Three bond pad stripping chemicals KOH, Aqua regia, and phosphoric acid were investigated in this study. Results obtained by dipping the chemicals at different temperatures, and time scales will be given. An optical microscope (OM) and scanning electron microscope (SEM) are used to observe the oxide conditions from the top view. To understand the mechanism of the oxide damage caused by wire bonding, a focused ion beam was used to observe the cross-section of the defect.


Author(s):  
K. Doong ◽  
J.-M. Fu ◽  
Y.-C. Huang

Abstract The specimen preparation technique using focused ion beam (FIB) to generate cross-sectional transmission electron microscopy (XTEM) samples of chemical vapor deposition (CVD) of Tungsten-plug (W-plug) and Tungsten Silicides (WSix) was studied. Using the combination method including two axes tilting[l], gas enhanced focused ion beam milling[2] and sacrificial metal coating on both sides of electron transmission membrane[3], it was possible to prepare a sample with minimal thickness (less than 1000 A) to get high spatial resolution in TEM observation. Based on this novel thinning technique, some applications such as XTEM observation of W-plug with different aspect ratio (I - 6), and the grain structure of CVD W-plug and CVD WSix were done. Also the problems and artifacts of XTEM sample preparation of high Z-factor material such as CVD W-plug and CVD WSix were given and the ways to avoid or minimize them were suggested.


Microscopy ◽  
2020 ◽  
Author(s):  
Kazuo Yamamoto ◽  
Satoshi Anada ◽  
Takeshi Sato ◽  
Noriyuki Yoshimoto ◽  
Tsukasa Hirayama

Abstract Phase-shifting electron holography (PS-EH) is an interference transmission electron microscopy technique that accurately visualizes potential distributions in functional materials, such as semiconductors. In this paper, we briefly introduce the features of the PS-EH that overcome some of the issues facing the conventional EH based on Fourier transformation. Then, we present a high-precision PS-EH technique with multiple electron biprisms and a sample preparation technique using a cryo-focused-ion-beam, which are important techniques for the accurate phase measurement of semiconductors. We present several applications of PS-EH to demonstrate the potential in organic and inorganic semiconductors and then discuss the differences by comparing them with previous reports on the conventional EH. We show that in situ biasing PS-EH was able to observe not only electric potential distribution but also electric field and charge density at a GaAs p-n junction and clarify how local band structures, depletion layer widths, and space charges changed depending on the biasing conditions. Moreover, the PS-EH clearly visualized the local potential distributions of two-dimensional electron gas (2DEG) layers formed at AlGaN/GaN interfaces with different Al compositions. We also report the results of our PS-EH application for organic electroluminescence (OEL) multilayers and point out the significant potential changes in the layers. The proposed PS-EH enables more precise phase measurement compared to the conventional EH, and our findings introduced in this paper will contribute to the future research and development of high-performance semiconductor materials and devices.


Author(s):  
C.S. Bonifacio ◽  
P. Nowakowski ◽  
R. Li ◽  
M.L. Ray ◽  
P.E. Fischione ◽  
...  

Abstract Fast and accurate examination from the bulk to the specific area of the defect in advanced semiconductor devices is critical in failure analysis. This work presents the use of Ar ion milling methods in combination with Ga focused ion beam (FIB) milling as a cutting-edge sample preparation technique from the bulk to specific areas by FIB lift-out without sample-preparation-induced artifacts. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 15 nm are obtained.


2017 ◽  
Vol 23 (3) ◽  
pp. 484-490 ◽  
Author(s):  
Andrey Denisyuk ◽  
Tomáš Hrnčíř ◽  
Jozef Vincenc Oboňa ◽  
Sharang ◽  
Martin Petrenec ◽  
...  

AbstractWe report on the mitigation of curtaining artifacts during transmission electron microscopy (TEM) lamella preparation by means of a modified ion beam milling approach, which involves altering the incident angle of the Ga ions by rocking of the sample on a special stage. We applied this technique to TEM sample preparation of a state-of-the-art integrated circuit based on a 14-nm technology node. Site-specific lamellae with a thickness <15 nm were prepared by top-down Ga focused ion beam polishing through upper metal contacts. The lamellae were analyzed by means of high-resolution TEM, which showed a clear transistor structure and confirmed minimal curtaining artifacts. The results are compared with a standard inverted thinning preparation technique.


1999 ◽  
Vol 5 (S2) ◽  
pp. 908-909
Author(s):  
J.L. Drown-MacDonald ◽  
B.I. Prenitzer ◽  
T.L. Shofner ◽  
L.A. Giannuzzi

Focused Ion Beam (FIB) specimen preparation for both scanning and transmission electron microscopy (SEM and TEM respectively) has seen an increase in usage over the past few years. The advantage to the FIB is that site specific cross sections (or plan view sections) may be fabricated quickly and reproducibly from numerous types of materials using a finely focused beam of Ga+ ions [1,2]. It was demonstrated by Prenitzer et al. that TEM specimens may be acquired from individual Zn powder particles by employing the FIB LO specimen preparation technique [3]. In this paper, we use the FIB LO technique to prepare TEM specimens from Mount Saint Helens volcanic ash.Volcanic ash from Mount Saint Helens was obtained at the Microscopy and Microanalysis 1998 meeting in Atlanta. TEM analysis of the ash was performed using the FIB lift out technique [1]. Ash powders were dusted onto an SEM sample stud that had been coated with silver paint.


Author(s):  
Steven B. Herschbein ◽  
Carmelo F. Scrudato ◽  
George K. Worth ◽  
Edward S. Hermann

Abstract Focused Ion Beam (FIB) modification for chip repair, layout verification, and internal signal probing has become an integral part of the process for bringing advanced products to market. As devices become more complex, with more levels of dense, thick upper power planes and tighter lower point-to-point wiring and device geometries, primary FIB access through the backside of the chip has become the only viable approach. And the pervasive switch to flip-chip solder bump mounting of chips to modules and chip to chip stacked die has made the backside editing approach ever more sensible by placing the unobstructed backside of the die within easy reach. Sample preparation for backside edit, however, has become a growing problem. Mechanical thinning of the silicon to speed trenching time can be problematic on highly stressed chips as there is a high risk of silicon cracking. Plus there are situations in which die strength must be preserved to enable the transfer of an edited die to a new substrate. While single point full thickness silicon editing has been demonstrated, the need to make multiple trenches for repetitive edits can be extremely time consuming when using conventional FIB bulk removal recipes. A single logic error often gets repeated in each core of a multi-core chip, and may need to be fixed at each location. Verification of existing SRAM and the introduction of embedded DRAM (eDRAM) for large blocks of L3 cache on high end microprocessors meant that the FIB lab would be called upon to provide layout checking services on a number of designs. Clearly, a better method for rapid mass silicon removal needed to be developed to keep multi-point backside editing viable. Through an extensive set of experiments we were able to develop a process that can sustain a removal rate of 10 million cubic microns of silicon per minute, enabling full thickness trenches in as little as 25 minutes. As will be shown, this preparation technique was successfully used to ensure the bit map descramble accuracy of multiple eDRAM array blocks in several cores, and to help evaluate test coverage.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000396-000404 ◽  
Author(s):  
Inderjit Singh ◽  
Shin Low ◽  
Syu Fu Song ◽  
Chen Shih Jung ◽  
Lin Ming San ◽  
...  

One of the biggest technology drivers in the semiconductor industry today is the fast transition from Au wire bonding to Cu wire bonding. The fast adaptation of Cu and Pd-coated Cu (PCC) wire has focused the whole packaging industry to develop understanding, equipment and processes that can produce a more reliable and robust Cu wire bonding technology. Although the fundamentals of wire bonding technology are very similar between Au and Cu wire bonding, there are a lot of new challenges in Cu wire bonding. Compared to Au wire bonding, Cu wire bonding needs different bond quality measures and metrology. Traditional ball diameter, ball height and shear measurements are not adequate to quantify a Cu wire bonding process. Some of the additional bond quality measures include pad material push out (pad splash), Al layer peel off (pad peel) and crack in the barrier and dielectric layer (pad crack). Another area that is quite different between Au and Cu is the reliability test requirement. In Au wire bonding, because of the fast intermetallic compound (IMC) growth rate, the HTS test is normally the hardest to pass. Due to the corrosion of Cu wire, the HAST test is the most challenging in Cu wire bonding. Reliability requirements still need more knowledge. In this paper, we conduct reliability tests for devices with 3 sets of wire bonding parameters. The bonded samples have IMC coverage between 94% and 97%, well above the industry level of 80%. The reliability (HAST) test passed for all samples at 96 hours. However, there are some failures in the HAST test at 192 hr. There are many factors that can influence reliability outcome including wire bonding and non-wire bonding related factors. The failure analysis identified two potential causes in our case. In one failure case, an abnormally high Chlorine level and void in molding compound were detected next to the failed bond while no Chlorine and void were detected elsewhere. In the 2nd failure case, the bonded ball seems to be off centered and results in poor bonded ball to pad interface. These two factors will be more tightly controlled in future tests to verify the reliability outcome. Intermetallic growth and phase transformation, aluminum oxide, and behavior of palladium in PdCu wire bonds are analyzed using transmission electron microscopy (TEM) of dual beam focused ion beam (FIB) thinned specimens. Results are compared to wire bonding measurement and reliability outcome.


2017 ◽  
Vol 23 (5) ◽  
pp. 1055-1060 ◽  
Author(s):  
Tae-Hoon Kim ◽  
Min-Chul Kang ◽  
Ga-Bin Jung ◽  
Dong Soo Kim ◽  
Cheol-Woong Yang

AbstractThe preparation of transmission electron microscopy (TEM) samples from powders is quite difficult and challenging. For powders with particles in the 1–5 μm size range, it is especially difficult to select an adequate sample preparation technique. Epoxy is commonly used to bind powder, but drawbacks, such as differential milling originating from unequal milling rates between the epoxy and powder, remain. We propose a new, simple method for preparing TEM samples. This method is especially useful for powders with particles in the 1–5 μm size range that are vulnerable to oxidation. The method uses solder as an embedding agent together with focused ion beam (FIB) milling. The powder was embedded in low-temperature solder using a conventional hot-mounting instrument. Subsequently, FIB was used to fabricate thin TEM samples via the lift-out technique. The solder proved to be more effective than epoxy in producing thin TEM samples with large areas. The problem of differential milling was mitigated, and the solder binder was more stable than epoxy under an electron beam. This methodology can be applied for preparing TEM samples from various powders that are either vulnerable to oxidation or composed of high atomic number elements.


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