High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

Author(s):  
X. Sun ◽  
C. D'Emic ◽  
C.-W. Cheng ◽  
A. Majumdar ◽  
Y. Sun ◽  
...  
2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


1996 ◽  
Vol 35 (Part 1, No. 3) ◽  
pp. 1751-1757 ◽  
Author(s):  
Ho Sung Cho ◽  
Dong Hoon Jang ◽  
Jung Kee Lee ◽  
Kyung Hyun Park ◽  
Jeong Soo Kim ◽  
...  

2000 ◽  
Vol 621 ◽  
Author(s):  
Min-Cheol Lee ◽  
Juhn-Suk Yoo ◽  
Kee-Chan Park ◽  
Sang-Hoon Jung ◽  
Min-Koo Han ◽  
...  

ABSTRACTWe have proposed and fabricated a new poly-Si TFT that employs selectively doped regions between the source and drain in order to reduce leakage current without the sacrifice of the on current. In the proposed poly-Si TFTs, the selectively doped regions where doping concentration is identical to that of source/drain, reduce the effective channel length during the on state. Under the off state, the selectively doped regions may reduce the lateral electric field induced in the depletion region near drain so that the leakage current reduces considerably. The experimental data of the proposed TFT shows that it has the high on-current, low leakage current and low threshold voltage when compared with conventional TFT. The fabrication steps for the proposed TFT are reduced because ion-implantation for source/drain and selectively doped regions is performed simultaneously prior to an excimer laser irradiation. It should be noted that, in the proposed TFT, only one excimer laser annealing is required while two excimer laser annealing steps are required in conventional TFT.


2013 ◽  
Vol 1561 ◽  
Author(s):  
Revathy Padmanabhan ◽  
Navakanta Bhat ◽  
S. Mohan ◽  
Y. Morozumi ◽  
Sanjeev Kaushal

ABSTRACTMetal-insulator-metal (MIM) capacitors for DRAM applications have been realized using TiO2/ZrO2/TiO2 (TZT) and AlO-doped TZT (TZAZT and TZAZAZT) dielectric stacks. High capacitance densities of about 46.6 fF/μm2 (for TZT stacks), 46.2 fF/μm2 (for TZAZT stacks), and 46.8 fF/μm2 (for TZAZAZT stacks) have been achieved. Low leakage current densities of about 4.9×10−8 A/cm2, 5.5×10−9 A/cm2, and 9.7×10−9 A/cm2 (at -1 V) have been obtained for TZT, TZAZT, and TZAZAZT stacks, respectively. We analyze the leakage current mechanisms at different electric field regimes, and compute the barrier heights. The effects of constant current stress and constant voltage stress on the device characteristics are studied, and excellent device reliability is demonstrated. We compare the device performance of the fabricated capacitors with other stacked high-k MIM capacitors reported in recent literature.


1997 ◽  
Vol 487 ◽  
Author(s):  
Z. Q. Shi ◽  
C. M. Stahle ◽  
P. Shu

AbstractOne of the critical issues in CdZnTe detector fabrication is the surface treatment. This will not only affect the electrical properties, such as leakage current, but also influence the physical properties, such as smoothness and adhesion between the metal and the semiconductor. The latter will determine the wire bonding yield. Historically, there has been a problem in achieving both low leakage current and excellent wire bonding yield. In this paper, we report our new approach to fabricate high performance doubled sided CdZnTe strip detectors. The new surface treatments involve chemical etching and post-annealing. The leakage current, interstrip resistance and energy resolution were studied as a function of different etchants/time and post-annealing temperature. It was found that a chemical etch with bromine in ethylene glycol (Br/EG) is suitable for the double sided strip detector process. Keeping a relatively smooth surface is critical for achieving a high yield of good strips. To improve the adhesion of the metal to CdZnTe for wire bonding, the detectors were annealed from 100 to 175°C for 10 hours. It has been observed that after annealing, not only has the strip leakage current decreased, but the interstrip resistance is increased for a temperature less than 150°C.


Author(s):  
Qian Yue ◽  
Wei Gao ◽  
Peiting Wen ◽  
Quan Chen ◽  
Mengmeng Yang ◽  
...  

Because of the in-gap defect levels, high deep ultraviolet (DUV) light absorption and low leakage current, the incorporation of 4H-silicon carbide (SiC) substrate has been confirmed to enhance the optoelectrical...


2011 ◽  
Vol 32 (7) ◽  
pp. 874-876 ◽  
Author(s):  
F. Medjdoub ◽  
M. Zegaoui ◽  
D. Ducatteau ◽  
N. Rolland ◽  
P. A. Rolland

2006 ◽  
Vol 53 (4) ◽  
pp. 923-925 ◽  
Author(s):  
M. Yamaguchi ◽  
T. Sakoda ◽  
H. Minakata ◽  
Shiqin Xiao ◽  
Y. Morisaki ◽  
...  

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