A High-k and Low Energy-disorder Spiro-nanopolymer Semiconductor

Gridization become the rising toolbox of cross-scale chemistry that update the organic pi-conjugated polymers into nano-polymers with a nano-scale persistence length that offer the cornerstone to overcome the molecular limitation for the high-performance fourth-generation semiconductors. In this work, spiro-polygridization indeed exhibit the ultralong persistence length of ~41 nm with the extraordinary semiconducting behaviors such as a hole mobility of 3.94 × 10-3 cm2 V-1 s-1 and an ultralow energy disorder (<50 meV) as well as the high dielectric constant (k = 8.43). Gridochemistry open a way to organic intelligent multimedia facing organic intelligence.

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Cross-Scale Synthesis of Organic High-k Semiconductors Based on Spiro-Gridized Nanopolymers

Research ◽

10.34133/2022/9820585 ◽

2022 ◽

Vol 2022 ◽

pp. 1-12

Author(s):

Dongqing Lin ◽

Wenhua Zhang ◽

Hang Yin ◽

Haixia Hu ◽

Yang Li ◽

...

Keyword(s):

Carrier Mobility ◽

Persistence Length ◽

Charge Trapping ◽

Hole Mobility ◽

Dielectric Constants ◽

Fourth Generation ◽

Photoelectric Conversion Efficiency ◽

Zero Field ◽

Photoelectric Conversion ◽

High Dielectric

High dielectric constants in organic semiconductors have been identified as a central challenge for the improvement in not only piezoelectric, pyroelectric, and ferroelectric effects but also photoelectric conversion efficiency in OPVs, carrier mobility in OFETs, and charge density in charge-trapping memories. Herein, we report an ultralong persistence length (lp≈41 nm) effect of spiro-fused organic nanopolymers on dielectric properties, together with excitonic and charge carrier behaviors. The state-of-the-art nanopolymers, namely, nanopolyspirogrids (NPSGs), are synthesized via the simple cross-scale Friedel-Crafts polygridization of A2B2-type nanomonomers. The high dielectric constant (k=8.43) of NPSG is firstly achieved by locking spiro-polygridization effect that results in the enhancement of dipole polarization. When doping into a polystyrene-based dielectric layer, such a high-k feature of NPSG increases the field-effect carrier mobility from 0.20 to 0.90 cm2 V-1 s-1 in pentacene OFET devices. Meanwhile, amorphous NPSG film exhibits an ultralow energy disorder (<50 meV) for an excellent zero-field hole mobility of 3.94×10−3 cm2 V−1 s−1, surpassing most of the amorphous π-conjugated polymers. Organic nanopolymers with high dielectric constants open a new way to break through the bottleneck of efficiency and multifunctionality in the blueprint of the fourth-generation semiconductors.

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Intrinsic high-k-low-loss dielectric polyimides containing ortho-position aromatic nitrile moieties: Reconsideration on Clausius-Mossotti Equation

Polymer Chemistry ◽

10.1039/d1py00084e ◽

2021 ◽

Author(s):

Tianwen Zhu ◽

Qiaoxi Yu ◽

Weiwen Zheng ◽

Runxin Bei ◽

Wenhui Wang ◽

...

Keyword(s):

Dielectric Loss ◽

High Performance ◽

High Dielectric Constant ◽

Polymer Materials ◽

Ortho Position ◽

Dielectric Polarization ◽

Low Loss ◽

Low Dielectric ◽

High K ◽

High Dielectric

Precision regulation of the dielectric polarization and dielectric loss of polymer materials, developing intrinsic high-performance polymers with high dielectric constant, low dielectric loss and excellent temperature resistance are very challenging....

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Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

10.31399/asm.cp.istfa2018p0300 ◽

2018 ◽

Author(s):

Seng Nguon Ting ◽

Hsien-Ching Lo ◽

Donald Nedeau ◽

Aaron Sinnott ◽

Felix Beaudoin

Keyword(s):

Failure Analysis ◽

High Performance ◽

Yield Loss ◽

Technology Development ◽

High Density ◽

High K ◽

Yield Learning ◽

Oxide Deposition ◽

Edge Profile ◽

High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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Fused Ambipolar Aza-isoindigos with NIR absorption

Organic Chemistry Frontiers ◽

10.1039/d0qo01495h ◽

2021 ◽

Author(s):

Liping Yao ◽

Danlei Zhu ◽

Hailiang Liao ◽

Sheik Haseena ◽

Mahesh kumar Ravva ◽

...

Keyword(s):

Organic Semiconductors ◽

High Performance ◽

Low Cost ◽

Light Weight ◽

The Past ◽

Pi Conjugated ◽

Nir Absorption ◽

Conjugated Organic Semiconductors

Due to their advantages of low-cost, light-weight, and mechanical flexibility, much attention has been focused on pi-conjugated organic semiconductors. In the past decade, although many materials with high performance has...

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Interfacial polarization-induced high-k polymer dielectric film for high-performance triboelectric devices

Nano Energy ◽

10.1016/j.nanoen.2020.105697 ◽

2021 ◽

Vol 82 ◽

pp. 105697

Author(s):

Minsoo P. Kim ◽

Chang Won Ahn ◽

Youngsu Lee ◽

Kyoungho Kim ◽

Jonghwa Park ◽

...

Keyword(s):

High Performance ◽

Dielectric Film ◽

Interfacial Polarization ◽

Polymer Dielectric ◽

High K

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32nm gate-first high-k/metal-gate technology for high performance low power applications

2008 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2008.4796770 ◽

2008 ◽

Cited By ~ 12

Author(s):

C. H. Diaz ◽

K. Goto ◽

H.T. Huang ◽

Yuri Yasuda ◽

C.P. Tsao ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Metal Gate ◽

High K

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Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

MRS Proceedings ◽

10.1557/opl.2013.585 ◽

2013 ◽

Vol 1538 ◽

pp. 291-302

Author(s):

Edward Yi Chang ◽

Hai-Dang Trinh ◽

Yueh-Chin Lin ◽

Hiroshi Iwai ◽

Yen-Ku Lin

Keyword(s):

Low Power ◽

Leakage Current ◽

High Speed ◽

High Performance ◽

Gate Oxide ◽

Chemical Cleaning ◽

Low Leakage ◽

Low Leakage Current ◽

High K ◽

Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

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