PERFORMANCE ANALYSIS OF DUAL METAL GATE MODIFIED SOURCE FULLY DEPLETED SOI MOSFET

2016 ◽  
Vol 5 (2) ◽  
pp. 7 ◽  
Author(s):  
TRIPATHI SANDEEP ◽  
MISHRA VIMAL KUMAR ◽  
CHAUHAN R.K ◽  
◽  
◽  
...  
Keyword(s):  
Performance Analysis ◽  
Metal Gate ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Dual Metal

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

2009 ◽  
Vol 53 (3) ◽  
pp. 256-265 ◽  
Author(s):  
Rathnamala Rao ◽  
Guruprasad Katti ◽  
Dnyanesh S. Havaldar ◽  
Nandita DasGupta ◽  
Amitava DasGupta
Keyword(s):  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Metal Gate ◽  
Fully Depleted ◽  
Dual Metal ◽  
Threshold Voltage Model

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

2014 ◽  
Vol 13 (2) ◽  
pp. 467-476 ◽  
Author(s):  
Gopi Krishna Saramekala ◽  
Abirmoya Santra ◽  
Mirgender Kumar ◽  
Sarvesh Dubey ◽  
Satyabrata Jit ◽  
...  
Keyword(s):  
Subthreshold Swing ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Subthreshold Current ◽  
Dual Metal

An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

2013 ◽  
Vol 60 ◽  
pp. 580-595 ◽  
Author(s):  
G.K. Saramekala ◽  
Abirmoya Santra ◽  
Sarvesh Dubey ◽  
Satyabrata Jit ◽  
Pramod Kumar Tiwari
Keyword(s):  
Threshold Voltage ◽  
Metal Gate ◽  
Short Channel ◽  
Soi Mosfet ◽  
Dual Metal ◽  
Threshold Voltage Model

scholarly journals Analytical Modeling and Simulation of Nanoscale Fully Depleted Dual Metal Gate SOI MOSFET

2019 ◽  
Vol 8 (10) ◽  
pp. 2946-2950
Keyword(s):  
Analytical Modeling ◽  
Cmos Technology ◽  
Step Function ◽  
Device Structure ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
New Device ◽  
Dual Metal ◽  
Dual Material

The demand and development of scaled semiconductors devices for upcoming challenges in VLSI technology is unending. CMOS technology plays a very important role in fulfilling this criterion. The conventional MOSFET exhibits short channel effects (SCE) and performance degradation when scaled down in the nanometer regime. In order to meet the required enhanced performance and to further increase the device density new materials and new device structures have been developed. This paper analyses the performance characteristics of one of such improved device structure i.e Fully Depleted Silicon over Insulator (FDSOI) which also incorporate the gate having two metals of different work function specifically called Dual Material Gate (DMG) SOI MOSFET. The analytical modeling for this device structure has also been carried out. The simulation characteristics match closely with analytical results and as the surface potential profile of the device has step function in ensures that this device effectively reduces the SCE.

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