Design and Calibration of MIMU Based on Chip Size Micro Inertial Sensors

2013 ◽  
Vol 849 ◽  
pp. 302-309
Author(s):  
Yun Xu ◽  
Xin Hua Zhu ◽  
Yu Wang
Keyword(s):  
High Performance ◽  
Inertial Sensors ◽  
Low Cost ◽  
Rapid Development ◽  
Experimental Result ◽  
Integrated Navigation ◽  
Bias Stability ◽  
Chip Size ◽  
Order Of Magnitude ◽  
On Chip

With rapid development of micro fabrication technology, the performance of MIMU has gradually improved. The MIMU introduced in this paper is based on the silicon micro machined gyroscope of type MSG7000D and accelerometer of type MSA6000. The volume of it is 3×3×3cm3, the mass is 68.5g and the power consumption is less than 1w. The experimental result shows that the bias stability of the gyroscope and accelerometer for each axis of the designed MIMU is less than 10°/h and 0.5mg respectively. For the non orthogonality in three axes of the structure, MIMU needs to be calibrated. After calibration, the measurement accuracy has improved by an order of magnitude. The designed MIMU can satisfy the requirement of high performance, low cost, light weight and small size for strap-down navigation system, thus it can be widely applied not only to the field of vehicles integrated navigation, attitude measurement but also to the fields of personal goods such as mobile, game consoles and so on.

Application of WeChat Mini-Program and Wi-Fi SoC in Agricultural IoT: A Low-Cost Greenhouse Monitoring System

2020 ◽  
Vol 63 (2) ◽  
pp. 325-337
Author(s):  
Lei Zhou ◽  
Zhengjun Qiu ◽  
Yong He
Keyword(s):  
Internet Of Things ◽  
Monitoring System ◽  
High Performance ◽  
Low Cost ◽  
Rapid Development ◽  
Sensor Nodes ◽  
Sensor Data ◽  
Smart Devices ◽  
Increasing Demand ◽  
On Chip

HighlightsA quick solution for developing and deploying custom agricultural IoT systems is proposed.Low-cost and high-performance devices are used for the design of sensor nodes.A mobile application based on WeChat Mini-Program is developed for device and data management.The proposed system brings convenience to both users and developers.Abstract. Increasing demand for automatic management of agricultural production and real-time remote monitoring has increased the need for smart devices, wireless technologies, and sensors. The internet of things (IoT) has emerged as a common technology for the management of multiple devices by multiple users. Some professional solutions are relatively difficult to implement for researchers who are interested in agricultural IoT but do not have requisite skills in computers and electronics. The unfriendliness of the user software limits the practical application of agricultural IoT in China. This article presents a simple solution based on an SoC (system-on-chip) and WeChat mini-program that focuses on low-cost hardware, rapid development, user-friendly application design, and helping developers get a quick start in building a DIY monitoring system. The ESP8266, a high-performance SoC, is used as the microcontroller and Wi-Fi module to transfer the sensor data to a remote server. A WeChat mini-program provides the graphical user interface, enabling users to manage devices and access data by clicking. Users can log into the system using their WeChat accounts and bind devices by scanning QR codes on the devices. Thus, the complex management and device binding in conventional systems can be overcome. The system is easy to be expand and has great potential for greenhouse environmental monitoring in China. Keywords: Greenhouse ambient monitoring, Internet of things, WeChat mini-program, Wi-Fi SoC.

scholarly journals Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

2021 ◽  
Author(s):  
Xiaohan Tao ◽  
Jianmin Pang ◽  
Jinlong Xu ◽  
Yu Zhu
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
Scientific Computing ◽  
Data Transfer ◽  
Performance Model ◽  
Experimental Result ◽  
Transfer Model ◽  
Scratchpad Memory ◽  
On Chip ◽  
Many Core

AbstractThe heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49$$\times$$ × and achieves an energy saving of 5.16$$\times$$ × on average.

scholarly journals On-Chip Integration of Pressure Plus 2-Axis (X/Z) Acceleration Composite TPMS Sensors with a Single-Sided Bulk-Micromachining Technique

Micromachines ◽  
2019 ◽  
Vol 10 (7) ◽  
pp. 473 ◽  
Author(s):  
Jiachou Wang ◽  
Fang Song
Keyword(s):  
Low Cost ◽  
Pressure Sensors ◽  
Silicon On Insulator ◽  
Automotive Electronics ◽  
Fabrication Technique ◽  
Front Side ◽  
Tire Pressure ◽  
Automobile Tire ◽  
Chip Size ◽  
On Chip

A novel on-chip integration of pressure plus 2-axis (X/Z) acceleration composite sensors for upgraded production of automobile tire pressure monitoring system (TPMS) is proposed, developed, and characterized. Herein, the X-axis accelerometer is with the cantilever beam-mass structure and is used for automatically identifying and positioning each of the four wheels. The IC-Foundry-Compatible low-cost batch fabrication technique of MIS (i.e., Micro-openings Inter-etch and Sealing) is employed to only fabricate the device from the front side of (111) silicon wafer, without double-sided micromachining, wafer bonding, complex Cavity-SOI (Silicon on Insulator) processing, and expensive SOI-wafer needed. Benefited from the single-wafer front-side fabrication technique on ordinary single-polished wafers, the fabricated composite TPMS sensor has the advantages of a small chip-size of 1.9 mm × 1.9 mm, low cross-talk interference, low-cost, and compatible process with IC-foundries. The fabricated pressure sensors, X-axis accelerometer and Z-axis accelerometer, show linear sensing outputs, with the sensitivities as about 0.102 mV/kPa, 0.132 mV/kPa, and 0.136 mV/kPa, respectively. Fabricated with the low-cost front-side MIS process, the fabricated composite TPMS sensors are promising in automotive electronics and volume production.

scholarly journals Recent Advances in Synthesis and Properties of Nitrated-Pyrazoles Based Energetic Compounds

Molecules ◽  
2020 ◽  
Vol 25 (15) ◽  
pp. 3475 ◽  
Author(s):  
Shijie Zhang ◽  
Zhenguo Gao ◽  
Di Lan ◽  
Qian Jia ◽  
Ning Liu ◽  
...  
Keyword(s):  
Energetic Materials ◽  
High Performance ◽  
High Efficiency ◽  
Low Cost ◽  
Rapid Development ◽  
Development Trend ◽  
High Heat ◽  
High Energy ◽  
Heat Of Formation ◽  
Energetic Compounds

Nitrated-pyrazole-based energetic compounds have attracted wide publicity in the field of energetic materials (EMs) due to their high heat of formation, high density, tailored thermal stability, and detonation performance. Many nitrated-pyrazole-based energetic compounds have been developed to meet the increasing demands of high power, low sensitivity, and eco-friendly environment, and they have good applications in explosives, propellants, and pyrotechnics. Continuous and growing efforts have been committed to promote the rapid development of nitrated-pyrazole-based EMs in the last decade, especially through large amounts of Chinese research. Some of the ultimate aims of nitrated-pyrazole-based materials are to develop potential candidates of castable explosives, explore novel insensitive high energy materials, search for low cost synthesis strategies, high efficiency, and green environmental protection, and further widen the applications of EMs. This review article aims to present the recent processes in the synthesis and physical and explosive performances of the nitrated-pyrazole-based Ems, including monopyrazoles with nitro, bispyrazoles with nitro, nitropyrazolo[4,3-c]pyrazoles, and their derivatives, and to comb the development trend of these compounds. This review intends to prompt fresh concepts for designing prominent high-performance nitropyrazole-based EMs.

SiP(System in Package) Solutions with Wafer Level Packaging Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002226-002253 ◽  
Author(s):  
In Soo Kang ◽  
Jong Heon (Jay) Kim
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Wafer Level ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Chip Size ◽  
Bonding Technology ◽  
Small Form Factor

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

3D Stacked Cache Data Management for Energy Minimization of 3D Chip Multiprocessor

2015 ◽  
Vol 3 (2) ◽  
pp. 264-268
Author(s):  
K. Suresh Kumar ◽  
S. Anitha ◽  
M. Gayathri
Keyword(s):  
Temperature Distribution ◽  
High Performance ◽  
Chip Multiprocessors ◽  
Electrical Power ◽  
Chip Multiprocessor ◽  
Energy Reduction ◽  
Experimental Result ◽  
Data Mapping ◽  
Promising Solution ◽  
On Chip

In this model a runtime cache data mapping is discussed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The suggested method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows energy reduction achieving up to 22.88% compared to an existing solution which considers only the temperature distribution.  New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation high performance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs with energy reduction achieving up to 19.55% by supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Compensation for Stochastic Error of Gyros in a Dual-axis Rotational Inertial Navigation System

2015 ◽  
Vol 69 (1) ◽  
pp. 169-182 ◽  
Author(s):  
Zhichao Zheng ◽  
Songlai Han ◽  
Jin Yue ◽  
Linglong Yuan
Keyword(s):  
Navigation System ◽  
High Performance ◽  
Inertial Navigation System ◽  
Inertial Sensors ◽  
Inertial Sensor ◽  
Low Cost ◽  
Inertial Navigation ◽  
Field Tests ◽  
Stochastic Error ◽  
Stochastic Errors

A dual-axis rotational Inertial Navigation System (INS) has received wide attention in recent years because of high performance and low cost. However, some errors of inertial sensors such as stochastic errors are not averaged out automatically during navigation. Therefore a Twice Position-fix Reset (TPR) method is provided to enhance accuracy of a dual-axis rotational INS by compensating stochastic errors. According to characteristics of an azimuth error introduced by stochastic errors of an inertial sensor in the dual-axis rotational INS, both an azimuth error and a radial-position error are much better corrected by the TPR method based on an optimised error propagation equation. As a result, accuracy of the dual-axis rotational INS is prominently enhanced by the TPR method, as is verified by simulations and field tests.

scholarly journals Validation of a Low-Cost Pavement Monitoring Inertial-Based System for Urban Road Networks

Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 3127
Author(s):  
Giuseppe Loprencipe ◽  
Flavio Guilherme Vaz de Almeida Filho ◽  
Rafael Henrique de Oliveira ◽  
Salvatore Bruno
Keyword(s):  
High Performance ◽  
Ride Comfort ◽  
Inertial Sensors ◽  
Inertial Sensor ◽  
Low Cost ◽  
Road Networks ◽  
Measurement Unit ◽  
Raspberry Pi ◽  
Urban Road ◽  
Comfort Index

Road networks are monitored to evaluate their decay level and the performances regarding ride comfort, vehicle rolling noise, fuel consumption, etc. In this study, a novel inertial sensor-based system is proposed using a low-cost inertial measurement unit (IMU) and a global positioning system (GPS) module, which are connected to a Raspberry Pi Zero W board and embedded inside a vehicle to indirectly monitor the road condition. To assess the level of pavement decay, the comfort index awz defined by the ISO 2631 standard was used. Considering 21 km of roads with different levels of pavement decay, validation measurements were performed using the novel sensor, a high performance inertial based navigation sensor, and a road surface profiler. Therefore, comparisons between awz determined with accelerations measured on the two different inertial sensors are made; in addition, also correlations between awz, and typical pavement indicators such as international roughness index, and ride number were also performed. The results showed very good correlations between the awz values calculated with the two inertial devices (R2 = 0.98). In addition, the correlations between awz values and the typical pavement indices showed promising results (R2 = 0.83–0.90). The proposed sensor may be assumed as a reliable and easy-to-install method to assess the pavement conditions in urban road networks, since the use of traditional systems is difficult and/or expensive.

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