Signature Analysis of Device Failure Mechanisms on 2.5D Package IC Devices

Device Failure ◽

Analysis Techniques ◽

3D Package ◽

Non Destructive ◽

Interconnect Technology ◽

Scanning Acoustic Microscope

Abstract The growing popularity of 2.5D SSIT (Stacked Silicon Interconnect Technology) & 3D package technology in the IC industry had made it more challenging for manufacturers and packaging assembly sites to perform failure analysis and identifying the root causes of failures. There had been some technical papers written on various failure analysis techniques on 2.5D SSIT and 3D IC packages using a variety of equipment for detecting and localizing failures [1, 2]. This paper explains a non-evasive, non-destructive approach of localizing failures on a 2.5D SSIT package by identifying and recognizing certain waveform patterns that the failing devices exhibit in the scanning acoustic microscope A-Scan and in Time domain reflectometry. There are noticeable waveform patterns that an analyst can recognize and used to determine certain types of failure mechanisms that may be present in the device. Please note that it is very important to use the exact same type of package sample when characterizing and comparing waveform patterns as package variability from vendor to vendor and material contents can certainly affect the results.

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

Time Domain Reflectometry Technique for Failure Analysis

10.31399/asm.cp.istfa2004p0616 ◽

2004 ◽

Author(s):

Teoh King Long ◽

Ko Yin Fern

Keyword(s):

Failure Analysis ◽

Time Domain ◽

Fault Isolation ◽

Reference Plane ◽

First Case ◽

Main Emphasis ◽

Plastic Ball ◽

Solder Balls ◽

Abstract In time domain reflectometry (TDR), the main emphasis lies on the reflected waveform. Poor probing contact is one of the common problems in getting an accurate waveform. TDR probe normalization is essential before measuring any TDR waveforms. The advantages of normalization include removal of test setup errors in the original test pulse and the establishment of a measurement reference plane. This article presents two case histories. The first case is about a Plastic Ball Grid Array package consisting of 352 solder balls where the open failure mode was encountered at various terminals after reliability assessment. In the second, a three-digit display LED suspected of an electrical short failure was analyzed using TDR as a fault isolation tool. TDR has been successfully used to perform non-destructive fault isolation in assisting the routine failure analysis of open and short failure. It is shown to be accurate and reduces the time needed to identify fault locations.

Non-Destructive Failure Analysis of Power Devices via Time- Domain Reflectometry

10.1109/case49439.2021.9551614 ◽

2021 ◽

Author(s):

Kanuj Sharma ◽

Simon Kamm ◽

Valentyna Afanasenko ◽

Kevin Munoz Baron ◽

Ingmar Kallfass

Keyword(s):

Failure Analysis ◽

Time Domain ◽

Power Devices ◽

Advanced Non-Destructive Fault Isolation Techniques for PCB Substrates Using Magnetic Current Imaging and Terahertz Time Domain Reflectometry

10.31399/asm.cp.istfa2018p0043 ◽

2018 ◽

Author(s):

Daechul Choi ◽

Yoonseong Kim ◽

Jongyun Kim ◽

Han Kim

Keyword(s):

Time Domain ◽

Quantum Interference ◽

Flip Chip ◽

Imaging System ◽

Fault Isolation ◽

Magnetic Current ◽

Isolation Techniques ◽

Super Conducting ◽

Abstract In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

10.31399/asm.cp.istfa2010p0233 ◽

2010 ◽

Author(s):

Kuo Hsiung Chen ◽

Wen Sheng Wu ◽

Yu Hsiang Shu ◽

Jian Chan Lin

Keyword(s):

Failure Analysis ◽

Failure Mechanisms ◽

Fault Localization ◽

Resistance Change ◽

The Real ◽

Analysis Techniques ◽

Analysis Technique ◽

Leakage Failure ◽

Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis ◽

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

10.31399/asm.cp.istfa1996p0277 ◽

1996 ◽

Author(s):

O. Diaz de Leon ◽

M. Nassirian ◽

C. Todd ◽

R. Chowdhury

Keyword(s):

Failure Analysis ◽

Large Scale ◽

Flip Chip ◽

Ultrasonic Waves ◽

Acoustic Microscopy ◽

Acoustic Microscope ◽

Chip Technology ◽

Ball Joints ◽

Non Destructive ◽

Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis ◽

Super-Conducting Quantum Interference Device Technique: 3-D Localization of a Short within a Flip Chip Assembly

10.31399/asm.cp.istfa2001p0069 ◽

2001 ◽

Author(s):

Kendall Scott Wills ◽

Omar Diaz de Leon ◽

Kartik Ramanujachar ◽

Charles P. Todd

Keyword(s):

Form Factor ◽

Failure Analysis ◽

Time Domain ◽

Quantum Interference ◽

Flip Chip ◽

Interfacial Region ◽

Precise Localization ◽

Super Conducting ◽

Accuracy Of Measurement

Abstract In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

Failure Analysis of Broken Stitch Bonds in TSSOP Packages Using Scanning Acoustic Microscopy (SAM) and Time Domain Reflectometry (TDR)

10.31399/asm.cp.istfa2004p0623 ◽

2004 ◽

Author(s):

Bilal Abd-AlRahman ◽

Corey Lewis ◽

Todd Simons

Keyword(s):

Failure Analysis ◽

Mechanical Stress ◽

Time Domain ◽

Open Circuit ◽

Acoustic Microscopy ◽

Scanning Acoustic Microscopy ◽

Root Cause ◽

Analysis Application

Abstract A failure analysis application utilizing scanning acoustic microscopy (SAM) and time domain reflectometry (TDR) for failure analysis has been developed to isolate broken stitch bonds in thin shrink small outline package (TSSOP) devices. Open circuit failures have occurred in this package due to excessive bending of the leads during assembly. The tools and their specific application to this technique as well as the limitations of C-SAM, TDR and radiographic analyses are discussed. By coupling C-SAM and TDR, a failure analyst can confidently determine whether the cause of an open circuit in a TSSOP package is located at the stitch bond. The root cause of the failure was determined to be abnormal mechanical stress placed on the pins during the lead forming operation. While C-SAM and TDR had proven useful in the analysis of TSSOP packages, it can potentially be expanded to other wire-bonded packages.

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

Electronic Package Failure Analysis Using TDR

10.31399/asm.cp.istfa2000p0277 ◽

2000 ◽

Author(s):

Dima A. Smolyansky

Keyword(s):

Failure Analysis ◽

Fault Location ◽

Measurement Accuracy ◽

Acoustic Imaging ◽

X Ray ◽

Analysis Techniques ◽

Bga Packages ◽

Impedance Profile ◽

Nature Of Time

Abstract The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

Advanced Fault Isolation Technique Using Electro-Optical Terahertz Pulse Reflectometry (EOTPR) for 2D and 2.5D Flip-Chip Package

10.31399/asm.cp.istfa2012p0021 ◽

2012 ◽

Author(s):

Lihong Cao ◽

Manasa Venkata ◽

Meng Yeow Tay ◽

Wen Qiu ◽

J. Alton ◽

...

Keyword(s):

Time Domain ◽

Flip Chip ◽

Fault Isolation ◽

Experimental Results ◽

Terahertz Pulse ◽

Isolation And Identification ◽

Isolation Technique ◽

Abstract Electro-optical terahertz pulse reflectometry (EOTPR) was introduced last year to isolate faults in advanced IC packages. The EOTPR system provides 10μm accuracy that can be used to non-destructively localize a package-level failure. In this paper, an EOTPR system is used for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems.