Optical Investigations of Temperature Effects in 14/16 nm FinFETs

Author(s):  
Ivo Vogt ◽  
Christian Boit ◽  
Tomonori Nakamura ◽  
Babak Motamedi

Abstract This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.

Author(s):  
Sagar Karki

Abstract With advancements in technology, it is nearly impossible to find the defects in integrated circuits without applying appropriate failure isolation techniques. Failure isolation is a critical step in identifying the physical defect on integrated circuits. This paper addresses the challenges imposed by floating node conditions on both analog and digital circuitry, and a case study for each circuit type is presented. Different approaches along with the challenges involved in isolating each case in a very timely manner are addressed. Finally, the usefulness of global isolation tools, such as PEM (Photon Emission Microscopy), FIB (Focused Ion Beam), and micro-probing, is also discussed.


2012 ◽  
Vol 730-732 ◽  
pp. 853-858
Author(s):  
Vicenç Torra ◽  
Carlota Auguet ◽  
Antonio Isalgue ◽  
Guillem Carreras ◽  
Francisco C. Lovey

The main interest focuses in the necessary tools for accurate simulation of the damper behavior in their application. It’s essential a well determined knowledge of the dissipated energy and of the hysteresis cycle shape for a correct simulation. The self-heating effects and the coupling between hysteresis and the relevant temperature effects associated to continuous cycling were studied. In particular, the experimental analysis concentrates in the action of cycling frequency on the hysteresis width and on the dissipated energy. The external and the self-heating temperature effects were studied. In particular, the convective actions of cooling in the conditioned air were visualized. The study of self-heating actions at extremely slow cycles, built by strain steps, shows minor latent heat dissipations in the entire sample. For trained samples, the temperature measurements establish that the transformation is “distributed” not “localized” in the complete sample.


2002 ◽  
Vol 743 ◽  
Author(s):  
M. Kuball ◽  
S. Rajasingam ◽  
A. Sarua ◽  
M. J. Uren ◽  
T. Martin ◽  
...  

ABSTRACTWe report on the in-situ measurement of temperature, i.e., self-heating effects, in multi-finger AlGaN/GaN HFETs grown on SiC substrates. Optical micro-spectroscopy was used to measure temperature with 1m spatial resolution. Thermal resistance (temperature rise per W/mm) was measured as a function of device pitch and gate finger width. There is significant thermal cross talk in multi-finger AlGaN/GaN HFETs and this needs to be seriously considered for device performance and ultimately device reliability. A comparison with theoretical modeling is presented. Uncertainties in modeling parameters currently make modeling less reliable than experimental temperature assessment of devices.


Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.


Author(s):  
Sergey Kuznetsov ◽  
Georgiy Teplov

In this paper, mathematical modeling of memristor has been discussed considering temperature effects and its variation during resistive switching. Temperature-affected parameters of memristor has been listed. A model of memristor has been carried out, including temperature influence on mobility of oxygen vacancies and self-heating effects. The model reveals that increasing temperature causes faster switching, also some problems of window function choice and model optimization have been discussed.


Author(s):  
A. Yurt ◽  
E. Ramsay ◽  
F. H. Köklü ◽  
M. S. Ünlü ◽  
B. B. Goldberg

Abstract We investigate a complementary objective lens design for correcting chromatic aberration in the use of a silicon aplanatic solid immersion lens for back-side photon emission microscopy of metal-oxide-semiconductor circuits. Our simulations demonstrate that the chromatic aberration due to material dispersion of aplanatic silicon solid immersion lenses can be reduced by more than an order of magnitude in the spectral window 1.5µm-2.1µm, providing new diffraction limited performance. On-axis and off-axis imaging performance of the proposed optical design is evaluated.


Author(s):  
Tibault Reveyrand ◽  
Walter Ciccognani ◽  
Giovanni Ghione ◽  
Olivier Jardel ◽  
Ernesto Limiti ◽  
...  

The present paper presents the transistor modeling work achieved in the GaN European project KorriGaN (“Key Organisation for Research in Integrated Circuits in GaN technology”). The KorriGaN project (2005–09) has released 29 GaN circuits such as high-power amplifiers (HPAs), low-noise amplifiers (LNAs), and switches. Modeling is one of the main key to reach successful designs. Therefore, nonlinear models of European GaN HEMT models have been developed. This work deals with characterization tools such as pulsed IV, pulsed [S] parameters, load-pull measurements, and measurement-based methods to perform GaN HEMT compact models parameters extraction. The present paper will describe the transistor modeling activities in KorriGaN for HPA designs (nonlinear models including trapping and/or self-heating effects) and LNA designs (nonlinear models and noise parameters).


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