Fault Isolation using Layout Pattern Analysis

2020 ◽  
Author(s):  
Atul Chittora ◽  
Neerja Bawaskar ◽  
Shobhit Malik ◽  
Monisa R Babu ◽  
Fadi Batarseh ◽  
...  
Keyword(s):  
Pattern Analysis ◽  
Fault Isolation ◽  
Test Results ◽  
Test Program ◽  
Design Information ◽  
Root Cause ◽  
Analysis Methodology ◽  
Exchange Format ◽  
Layout Structure ◽  
Program Information

Abstract Many fabless customers do not share the design information such as LEF/DEF (Library Exchange Format and Design Exchange Format), design netlist, and test program information with foundries because they contain proprietary IP. Determining the root-cause of defects on such products only based on Sort test results and no scan diagnostics [1] for logic chips can be quite challenging. This paper presents a new layout pattern analysis methodology to isolate the failing weak layout structure using only the sort test results and the product GDS layout.

Vdd Leakage Analysis by a Combination of Various Failure Analysis Techniques

2008 ◽  
Author(s):  
Z. G. Song ◽  
S. B. Ippolito ◽  
P. J. McGinnis ◽  
A. Shore ◽  
B. Paulucci ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Hot Spot ◽  
Fault Isolation ◽  
Physical Analysis ◽  
Analysis Techniques ◽  
Root Cause ◽  
Defect Location ◽  
Analysis Methodology ◽  
Analysis Process ◽  
Leakage Failure

Abstract It is generally accepted that the fault isolation of Vdd short and leakage can be globally addressed by liquid crystal analysis (LCA), photoemission analysis and/or laser stimulating techniques such as OBIRCH or TIVA. However, the hot spot detected by these techniques may be a secondary effect, rather than the exact physical defect location. Further electrical probing with knowledge of the circuit schematic and layout may still be required to pinpoint the exact physical defect location, so that a suitable physical analysis methodology can be chosen to identify the root cause of the failure. This paper has described a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques and finally the root cause of the Vdd leakage was identified.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

Root Cause Analysis Techniques Using Picosecond Time Resolved LADA

2014 ◽  
Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Picosecond Laser ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
Time Resolved ◽  
Cause Analysis ◽  
Root Cause ◽  
Design And Manufacturing ◽  
Multiple Interactions ◽  
Established Technique

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

2002 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch ◽  
Michael Zimin
Keyword(s):  
Failure Analysis ◽  
Process Variations ◽  
Fault Isolation ◽  
Operating Conditions ◽  
Detection Sensitivity ◽  
Isolation Technique ◽  
Root Cause ◽  
Emission Microscopy ◽  
Failure Location ◽  
Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

Failure Investigation of 1st Stage Buckets From Frame 3002, 10 MW Gas Turbine Unit

2011 ◽  
Author(s):  
Girish M. Shejale ◽  
David Ross
Keyword(s):  
Gas Turbine ◽  
Test Results ◽  
High Carbon ◽  
High Carbon Content ◽  
Metallurgical Investigation ◽  
Root Cause ◽  
Failure Investigation ◽  
Surface Failure ◽  
Grain Boundary Embrittlement ◽  
Industrial Gas Turbine

The 1st stage buckets in Frame 3002, 10 MW industrial gas turbine experienced premature failures. The buckets failed unexpectedly much earlier than the designed bucket life. Bucket material is Inconel 738, with platinum-aluminized coating on the surface. Failure investigation of the buckets was performed to know the root cause of the failure. The failure investigation primarily comprised of metallurgical investigation. The results of the metallurgical investigation were co-related with the unit operational history. This paper provides an overview of 1st stage buckets investigation. The metallurgical investigation performed concluded prime failure mechanism due to high carbon content of bucket material and improper heat treatment. The bucket coating was initially damaged during the first loading and fracture occurred due to grain boundary embrittlement in short span of service. The metallurgical tests performed included Visual inspection, Scanning Electron Microscopy (SEM), Energy Dispersive Analysis of X-ray (EDS), Chemical analysis, Tensile test and Hardness survey. The test results, discussions and conclusions are presented in this paper.

Communications-Based Train Control: Test Program Challenges

2018 ◽  
Author(s):  
Kenneth Diemunsch ◽  
Keith Altamirano
Keyword(s):  
Field Tests ◽  
Field Testing ◽  
Smooth Transition ◽  
Testing Time ◽  
Acceptance Test ◽  
Test Program ◽  
Root Cause ◽  
Train Control ◽  
Transit Agencies ◽  
Program Challenges

This paper discusses two real-world challenges faced by Communications-Based Train Control (CBTC) testing programs. a) Why is it that even after a successful complete system Factory Acceptance Test (FAT), the performance of the CBTC system during the first few months of field tests is prone to frequent failures? On some projects, it may be months between a successful FAT and the first operation in CBTC mode. b) How accurately and efficiently can the root cause of failures during the field tests be identified and how could a test program be improved to have a smooth transition from field testing to revenue service. Unlike commissioning a conventional signaling system, where after circuit break down and operation testing are completed, the system works well during revenue service, CBTC projects experience an additional round of ‘surprises’ when the system is put in service after months or years of testing [1]. This comment is valid for both new lines and signaling upgrade projects, it should be noted that signaling upgrade projects are more prone to ‘surprises’ due to the limited track access which reduces testing time. Even though the final test results prior to revenue service indicate no ‘showstoppers’, once system is placed in service, it is common to unearth major issues that impact sustainable revenue operation. Though, as it should, this often comes as a surprise to transit agencies installing CBTC for the first time, it is almost accepted as fate by most of the experienced CBTC engineers. This paper describes the tests performed prior to placing system in revenue service and analyzes some of the issues experienced. Detailed information regarding the field tests can be found in [2]. Description of possible mitigations used by CBTC suppliers and transit agencies are included, as well as likely reasons for such a predictable pattern on CBTC projects. Finally, ideas about how to continue improving the mitigation to minimize the risk of major system issues are presented.

scholarly journals Finite-element analysis and structure optimization of X-O composite seal of cone bit

2020 ◽  
Vol 12 (5) ◽  
pp. 168781402091868
Author(s):  
Shuang Jing ◽  
Anle Mu ◽  
Yi Zhou ◽  
Ling Xie
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Structural Parameters ◽  
Structure Optimization ◽  
Seal Ring ◽  
Test Results ◽  
Element Analysis ◽  
Root Cause ◽  
Sealing Performance ◽  
Distribution Of Stress

The seal is the key part of the cone bit. To reduce the failure probability, a new seal was designed and studied. The sealing performance and structure optimization of the X-O composite seal was analyzed and compared by finite-element analysis. The stress and contact pressure were analyzed to establish the main structural parameters that affect sealing performance and the direction of the structural optimization. By optimizing these structural parameters, including the height, and the radial and axial arc radii, an optimized structure is obtained. The results show that (1) the X-O composite seal can meet the seal requirement, the excessive height of the X seal ring is the root cause of the uneven distribution of stress, pressure, and distortion. (2) A new seal structure is obtained, the distribution of pressure and stress is reasonable and even, and the values of stress and pressure are reduced to avoid distortion and reduce the wear. Finally, the field test results of the X-O composite seal of cone bit showed that the service life of the bit bearing increased by 16% on average and the drilling efficiency increased by 11% on average compared with the original cone bit with the O seal ring.

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