Low-Power and High-Speed Configurable Arithmetic and Logic Unit

2019 ◽  
pp. 355-363
Author(s):  
Naveen Kumar Kabra ◽  
Zuber M. Patel
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Unit

A new design of a low-power reversible Vedic multiplier

2020 ◽  
Vol 18 (03) ◽  
pp. 2050002
Author(s):  
Meysam Rashno ◽  
Majid Haghparast ◽  
Mohammad Mosleh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Reversible Logic ◽  
Arithmetic Circuits ◽  
Quantum Cost ◽  
Computing Systems ◽  
Vedic Multiplier ◽  
Wide Range ◽  
Logic Unit

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

scholarly journals Design and Performance Analysis of Low Power High Speed Adder and Multiplier Using MTCMOS in 90nm, 70nm, 25nm and 18nm Regime

2021 ◽  
Author(s):  
Kalpana.K ◽  
Paulchamy. B ◽  
Priyadharsini. R ◽  
Arun Kumar Sivaraman ◽  
Rajiv Vincent ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Arithmetic Operation ◽  
Low Power Consumption ◽  
Vlsi Technology ◽  
And Performance ◽  
System Designs ◽  
Speed Propagation ◽  
Low Power Multiplier ◽  
Logic Unit

Nowadays, VLSI technology mainly focused on High-Speed Propagation and Low Power Consumption. Addition is an important arithmetic operation which plays a major role in digital application. Adder is act as an important role in the applications of signal processing, in memory access address generation and Arithmetic Logic Unit. When the number of transistors increases in system designs, makes to increase power and complexity of the circuit. One of the dominant factors is power reduction in low power VLSI technology and to overcome the power dissipation in the existing adder circuit, MTCMOS technique is used in the proposed adder. The design is simulated in 90nm, 70nm, 25nm and 18nm technology and then comparison is made between existing and proposed system in the context of energy, area and delay. In this comparison, the efficiency metrics power and delay are found to be reduced 20% from the existing adder and the proposed adder is used for the design of low power multiplier.

scholarly journals A Novel Design and Evaluation of a Low Power Efficient Fault-Tolerant Reversible ALU Using QCA: Applications of Nanoelectronics

2021 ◽  
Author(s):  
Mary Swarna Latha Gade ◽  
Rooban S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fault Tolerant ◽  
Logic Gates ◽  
Reversible Logic ◽  
Functional Verification ◽  
Logical Operations ◽  
Arithmetic Logic Unit ◽  
Reversible Alu ◽  
Logic Unit

Abstract Reversible logic based on Quantum-dot Cellular Automata (QCA) is the most requirement for achieving nano-scale architecture that promises significantly high device integration density, high-speed calculation, and low power consumption. The arithmetic logic unit (ALU) is the significant component of a processor for processing and computing. The primary objective of this work is to develop a multi-layer fault-tolerant arithmetic logic unit using reversible logic in QCA technology. Additionally, the reversible ALU has divided into arithmetic (RAU) and a logic unit (RLU). A reversible 2:1 MUX using the Fredkin gate has been implemented to select either the arithmetic or logical operations. Besides, to improve the efficiency of arithmetic operations, a novel QCA reversible full adder is implemented. To build the ALU, fault-tolerant reversible logic gates are used. The proposed reversible multilayer QCA ALU is designed to carry out eight arithmetic and sixteen logical operations with a minimum number of gates, constant inputs, and garbage outputs compared to the existing works. The functional verification and simulation of the presented circuits are assessed by the QCADesigner tool.

scholarly journals Multilayer Structure of a New Portable, Low-Cost and Reversible Arithmetic and Logic Unit using High-Speed and Low-Power “QCA” Technology with Good-Scalability.

2019 ◽  
Vol 8 (4) ◽  
pp. 10568-10575
Keyword(s):  
Cellular Automata ◽  
Low Power ◽  
Integrated Circuit ◽  
Multilayer Structure ◽  
High Speed ◽  
Low Cost ◽  
Cmos Technology ◽  
Reversible Logic ◽  
Clock Frequency ◽  
Logic Unit

All nano-technologies including “QCA” (Quantumdot Cellular Automata) is widely used in today‟s world to reduce the power dissipation, area and delay. “QCA” is a magnify technology with huge advantages such as: high-speed, highdensity, faster-switching and higher clock-frequency which is rapidly used for Integrated-Circuit (“IC”) design. Quantum-dot Cellular Automata is an useful and appropriate alternative of the “CMOS-technology” because of its various advantages such as: it‟s high-frequency, less power leakage and less required area. An “ALU” (arithmetic and logic unit) is applying for all types of arithmetic-logical performances and it widely used in digital circuits for all types of arithmetic and logical operations. The reversible-Logic an authentic solution in low-power and low-cost technology. This paper presents a latest 3-D or multilayer structure of ALU using reversible-computing and also non-reversible logic which gives a comparative outcome with low supply-power and delay. The complexity of the formation and the engrossed size of this model is low. „AND-Gate‟, „OR-Gate‟ ,„XOR-Gate‟ and the reversible „TSG-Gate‟ and also the non-reversible model of “FullAdder” are used to design the suggested model of this paper through the “QCA Designer” software (for simulation).This design reduce the size of the model up to 0.11 µm2 with three layers which is also compared to the formation in the “Xilinx” software.

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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