scholarly journals Prominent Speed Low Power Compressor Based Multiplier for Proficient VLSI Architecture

2020 ◽  
pp. 228-232
Author(s):  
V. Supraja ◽  
S. Sandhya ◽  
Y. Lavanya ◽  
M. Bhavana ◽  
V. Keerthana
Keyword(s):  
Low Power ◽  
Significant Role ◽  
Electronic Circuit ◽  
Vlsi Architecture ◽  
Computation Time ◽  
Cmos Technology ◽  
Operating Modes ◽  
Digital Electronics ◽  
Almost All

In the recent years the computational units are optimized to reduce the computation time. Multiplier is an electronic circuit used in digital electronics and has a significant role in vlsi applications. The 4:2 compressors have a flexibility of switching between exact and appropriate operating modes. In the appropriate mode the dual quality compressors provides higher speeds and consumes low power. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The efficiencies of these compressors are used in another type of multiplier and are evaluated in 45 nm standard CMOS technology. By comparing the parameters of this multiplier with those of appropriate multipliers, the results indicate a better in almost all the aspects.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

PRINCIPLE OF AUTONOMY IN LETTER OF CREDIT: MALAYSIAN PRACTICE

2012 ◽  
Vol 19 (2) ◽  
Author(s):  
Rosmawani Che Hashim ◽  
Ahmad Azam Othman ◽  
Akhtarzaite Abdul Aziz
Keyword(s):  
International Trade ◽  
Significant Role ◽  
Case Law ◽  
Huge Amount ◽  
Letter Of Credit ◽  
Relevant Case ◽  
Method Of Payment ◽  
Almost All

The term letter of credit (LC) is not uncommon in international trade as it is the most frequently used method of payment by seller and buyer in their sales contract. LC serves its significant role by facilitating payment between buyer and seller from different countries, who are always prejudiced towards each other on the issue of payment, especially when the deal involves a huge amount of money. By using LC, the seller and buyer will be represented by their own bankers whose function, among others is to issue an LC for the buyer and pay on presentation of seller’s documents which strictly comply to LC requirements. It is well-known that LC is governed by the principle of autonomy or also referred to as the principle of independence1 which indicates LC, being a contract of payment is totally separate from the underlying sales contract. Banks are concerned with documents only and not with the goods. LC transaction can be governed by the Uniform Custom and Practice for Documentary Credit, known as the UCP through express incorporation which provides the rules relating to LC matters and is adopted in almost all LC transactions. This paper discusses the nature, background and significance of principle of autonomy in LC transaction. In elaborating the provisions on the principle of autonomy in the UCP 600, comparisons between relevant articles in the UCP 500 are highlighted. The discussion also focuses on relevant case law and on the application of the autonomy principle in conventional and Islamic LC. The paper concludes with the finding that Malaysian bankers fully subscribe to the principle of autonomy as outlined by the UCP 600.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

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