scholarly journals Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

2021 ◽  
Author(s):  
Pil Woo (Peter) Chun

Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach

2021 ◽  
Author(s):  
Pil Woo (Peter) Chun

Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach


Blood ◽  
2006 ◽  
Vol 108 (11) ◽  
pp. 3402-3402
Author(s):  
Carina S. Debes Marun ◽  
Vincent Sieben ◽  
Patrick M. Pilarski ◽  
Tony Reiman ◽  
Andrew R. Belch ◽  
...  

Abstract Interphase fluorescence in situ hybridization (FISH) is widely used as a diagnostic tool for known genetic abnormalities due to its sensitivity for detection of cryptic aberrations, such as t(4;14)(p16;q32) in multiple myeloma (MM). In many cancers, chromosomal abnormalities are prognostic indicators that also predict response to therapy. Tests to determine the type and extent of these abnormalities are increasingly essential for more informed diagnosis and choice of treatment strategies. However the cost and complexity of the current FISH protocols, and the variability arising from differences in technical approach and subjective evaluation of hybridization patterns has compromised its widespread utilization. To create a standardized platform that will be accurate, robust, cost-effective and easy to use in any clinical setting, we have developed a microfluidic platform that enables simultaneous assessment of 10 chromosomal abnormalities or 10 patients, on a single chip. Microfluidic chips are hybrid polymer/glass microsystems with miniaturized networks of wells and channels, incorporating valves, heaters and fluidic control. The 10 channel microfluidic chip used here is the size of a microscope slide. Each channel requires only 1/10 the amount of probe used in conventional FISH, thus substantially reducing the cost per test. All the probes tested gave comparable results to conventional testing. Three cell lines and three ex-vivo PBMC samples from MM patients were tested against four different chromosomal probe sets, to detect translocation (4:14), any 14q32 translocation, deletion of chromosome 13 or deletion of p53. We used a mixture of patient sample and cell line to test the robustness of our technology and were able to successfully distinguish abnormal patterns with percentages that were comparable to FISH on microscope slides. On-chip FISH was highly reliable with consistent results in multiple test runs. To automate the process of reading slide, a computer vision algorithm was developed to provide a quantitative and objective measure of staining patterns, and to eventually eliminate the requirement for human intervention. This strategy uses artificial intelligence to distinguish probe from background staining, to identify and quantify the number of cells with different chromosomal patterns. This visual processing algorithm has been validated against human interpretation and provides a sensitive and unbiased method to distinguish signal and noise within stained cells. Although reliable and reproducible hybridization occurred in as little as four hours, to further reduce the time required for FISH testing, methods to enhance the hybridization were examined. These included chip designs that implemented mechanical or electrokinetic pumping. Both methods improved the hybridization and are currently being optimized. On-chip FISH appears to be versatile, fast and inexpensive, making fully automated FISH testing a possibility. Compared to conventional methods, these first iterations of on-chip FISH provide a 10-fold higher throughput and a 10 fold reduction in the cost of testing. On-chip FISH technology holds promise for sophisticated and cost-effective screening of cancer patients at every clinic visit in any health care setting, thus facilitating the delivery of personalized cancer care targeted to the genetic characteristics of each individual. Funded by CIHR, NSERC and Western Economic Diversification.


2015 ◽  
Vol 19 (1) ◽  
pp. 14 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz

Modern day field programmable gate arrays(FPGAs) have very huge and versatile logic resources resulting inthe migration of their application domain from prototypedesigning to low and medium volume production designing.Unfortunately most of the work pertaining to FPGAimplementations does not focus on the technology dependentoptimizations that can implement a desired functionality withreduced cost. In this paper we consider the mapping of simpleripple carry fixed-point adders (RCA) on look-up table (LUT)based FPGAs. The objective is to transform the given RCABoolean network into an optimized circuit netlist that canimplement the desired functionality with minimum cost. Weparticularly focus on 6-input LUTs that are inherent in all themodern day FPGAs. Technology dependent optimizations arecarried out to utilize this FPGA primitive efficiently and theresult is compared against various adder designs. Theimplementation targets the XC5VLX30-3FF324 device fromXilinx Virtex-5 FPGA family. The cost of the circuit is expressedin terms of the resources utilized, critical path delay and theamount of on-chip power dissipated. Our implementation resultsshow a reduction in resources usage by at least 50%; increase inspeed by at least 10% and reduction in dynamic powerdissipation by at least 30%. All this is achieved without anytechnology independent (architectural) modification.


2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000797-000816
Author(s):  
Mark Vandermeulen ◽  
Andrew Smith ◽  
Ron Csermak

Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures. A robust, innovative approach, suitable for supporting low- to medium-volume applications, has been developed which avoids the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well-suited for designs incorporating multiple IC's from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time to market. This presentation will describe this novel 3D packaging approach, and how it can be used in conjunction with discrete and integrated passive components to address package designs where size, weight, and/or performance are at a premium.


1993 ◽  
Vol 323 ◽  
Author(s):  
H. F. Lockwood ◽  
C. A. Armiento

AbstractThe principal driver behind advanced hardware development in the communications and computer industries can be reduced to an optimal set of parameters related to performance, cost and reliability. High performance systems typically have high functional density. For example, the continuing trend of VLSI is toward reduced feature size, increased wiring density and larger chip size to achieve increasingly higher levels of on-chip functionality. At some point in the cost structure, however, the single chip solution is no longer viable, and monolithic integration gives way to hybrid integration. In this respect, the multichip module fills a void in the packaging/ integration hierarchy between the ever-larger single chip and the printed wiring board.An analogous situation is emerging in optoelectronics. The single chip package with its relatively low system functionality and high cost is giving way to the multi-technology module that integrates optical and electronic functions within a single package. One of the most interesting approaches to the multi-technology module uses a silicon substrate as the platform for hybrid integration of electronics and optoelectronics. It will be argued that this “silicon waferboard” approach is the cost-effective route to manufacturability of high-performance modules for communications and computer systems. Enhanced reliability follows from applying standard IC processing technology at the platform level in the packaging hierarchy.


2014 ◽  
Vol 121 (4) ◽  
pp. 899-903 ◽  
Author(s):  
Lester Lee ◽  
Nicolas K. K. King ◽  
Dinesh Kumar ◽  
Yew Poh Ng ◽  
Jai Rao ◽  
...  

Object The choice of programmable or nonprogrammable shunts for the management of hydrocephalus after aneurysmal subarachnoid hemorrhage (SAH) remains undefined. Variable intracranial pressures make optimal management difficult. Programmable shunts have been shown to reduce problems with drainage, but at 3 times the cost of nonprogrammable shunts. Methods All patients who underwent insertion of a ventriculoperitoneal shunt for hydrocephalus after aneurysmal SAH between 2006 and 2012 were included. Patients were divided into those in whom nonprogrammable shunts and those in whom programmable shunts were inserted. The rates of shunt revisions, the reasons for adjustments of shunt settings in patients with programmable devices, and the effectiveness of the adjustments were analyzed. A cost-benefit analysis was also conducted to determine if the overall cost for programmable shunts was more than for nonprogrammable shunts. Results Ninety-four patients underwent insertion of shunts for hydrocephalus secondary to SAH. In 37 of these patients, nonprogrammable shunts were inserted, whereas in 57 programmable shunts were inserted. Four (7%) of 57 patients with programmable devices underwent shunt revision, whereas 8 (21.6%) of 37 patients with nonprogrammable shunts underwent shunt revision (p = 0.0413), and 4 of these patients had programmable shunts inserted during shunt revision. In 33 of 57 patients with programmable shunts, adjustments were made. The adjustments were for a trial of functional improvement (n = 21), overdrainage (n = 5), underdrainage (n = 6), or overly sunken skull defect (n = 1). Of these 33 patients, 24 showed neurological improvements (p = 0.012). Cost-benefit analysis showed $646.60 savings (US dollars) per patient if programmable shunts were used, because the cost of shunt revision is a lot higher than the cost of the shunt. Conclusions The rate of shunt revision is lower in patients with programmable devices, and these are therefore more cost-effective. In addition, the shunt adjustments made for patients with programmable devices also resulted in better neurological outcomes.


2016 ◽  
Vol 24 (05) ◽  
pp. 1750062 ◽  
Author(s):  
DIVYA BAJPAI TRIPATHY ◽  
ANURADHA MISHRA

Gemini surfactants are presently gaining attention due to their unusual self-assembling characteristics and incomparable interfacial activity. Current research work involves the cost-effective microwave (MW) synthesis of waste soybean oil-based gemini imidazolinium surfactants (GIS) having a carbonate linkage in its spacer moiety. Structural characterizations of the materials have been done using FT-IR, 1H-NMR and [Formula: see text]C-NMR. Using indigenous and natural material as base and MW as energy source for synthesizing the GIS with easily degradable chemical moiety make them to be labeled as green surfactants.


Author(s):  
James F. Mancuso

IBM PC compatible computers are widely used in microscopy for applications ranging from control to image acquisition and analysis. The choice of IBM-PC based systems over competing computer platforms can be based on technical merit alone or on a number of factors relating to economics, availability of peripherals, management dictum, or simple personal preference.IBM-PC got a strong “head start” by first dominating clerical, document processing and financial applications. The use of these computers spilled into the laboratory where the DOS based IBM-PC replaced mini-computers. Compared to minicomputer, the PC provided a more for cost-effective platform for applications in numerical analysis, engineering and design, instrument control, image acquisition and image processing. In addition, the sitewide use of a common PC platform could reduce the cost of training and support services relative to cases where many different computer platforms were used. This could be especially true for the microscopists who must use computers in both the laboratory and the office.


Phlebologie ◽  
2007 ◽  
Vol 36 (06) ◽  
pp. 309-312 ◽  
Author(s):  
T. Schulz ◽  
M. Jünger ◽  
M. Hahn

Summary Objective: The goal of the study was to assess the effectiveness and patient tolerability of single-session, sonographically guided, transcatheter foam sclerotherapy and to evaluate its economic impact. Patients, methods: We treated 20 patients with a total of 22 varicoses of the great saphenous vein (GSV) in Hach stage III-IV, clinical stage C2-C5 and a mean GSV diameter of 9 mm (range: 7 to 13 mm). We used 10 ml 3% Aethoxysklerol®. Additional varicoses of the auxiliary veins of the GSV were sclerosed immediately afterwards. Results: The occlusion rate in the treated GSVs was 100% one week after therapy as demonstrated with duplex sonography. The cost of the procedure was 207.91 E including follow-up visit, with an average loss of working time of 0.6 days. After one year one patient showed clinical signs of recurrent varicosis in the GSV; duplex sonography showed reflux in the region of the saphenofemoral junction in a total of seven patients (32% of the treated GSVs). Conclusion: Transcatheter foam sclerotherapy of the GSV is a cost-effective, safe method of treating varicoses of GSV and broadens the spectrum of therapeutic options. Relapses can be re-treated inexpensively with sclerotherapy.


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