Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Modern CMOS imaging devices are present everywhere, in the form of line, area and depth scanners. These image devices can be used in the automotive field, in industrial applications, in the consumer’s market, and in various medical and scientific areas. Particularly in industrial and scientific applications, the low-light noise performance or the high dynamic-range features are often the cases of interest, combined with low power dissipation and high frame rates. In this sense, the noise floor performance and the power consumption are the focus of this work, given that both are interlinked and play a direct role in the remaining sensor features. It is known that thermal and flicker noise sources are the main contributors to the degradation of the sensor performance, concerning the sensor output image noise. This paper presents an indirect way to reduce both the thermal and the flicker noise contributions by using thin-oxide low voltage supply column readout circuits and fast 3rd order incremental sigma-delta converters with noise shaping capabilities (to provide low noise output digital samples—74 μVrms; 0.7 e−rms; at 105 μV/e−), and thus performing correlated double sampling in a short time (19 μs), while dissipating significant low power (346 μW). Throughout the extensive parametric transistor-level simulations, the readout path produced 1.2% non-linearity, with a competitive saturation capacity (6.5 ke−) pixel. In addition, this paper addresses the readout parallelism as the main point of interest, decoupling resolution from the image noise and the frame rate, at virtually any array resolution. The design and simulations were performed with Virtuoso 6.17 tools (Cadence Design Systems, San Jose, CA, USA) using Spectre models from TS18IS Image Sensor 0.18 µm Process Development Kit (Tower Jazz Semiconductor, Migdal Haemek, Israel).

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Development of a new distributed hybrid seismic-electrical data acquisition station based on system–on-a-programmable-chip technology

10.5194/gi-2019-12 ◽

2019 ◽

Author(s):

Qisheng Zhang ◽

Wenhao Li ◽

Feng Guo ◽

Zhenzhong Yuan ◽

Shuaiqing Qiao ◽

...

Keyword(s):

Low Power ◽

Data Acquisition ◽

High Precision ◽

Data Transmission ◽

Dynamic Range ◽

Low Voltage ◽

Low Noise ◽

Transmission Protocol ◽

Control Board ◽

Electrical Data

Abstract. In the past few decades, with the continuous advancement of technology, seismic-electrical instruments have developed rapidly. However, complex and harsh exploration environments have put forward higher requirements and severe challenges for traditional geophysical exploration methods and instruments. Therefore, it is extremely urgent to develop new high-precision exploration instruments and data acquisition systems. In this study, a new distributed seismic-electrical hybrid acquisition station is developed using system-on-a-programmable-chip (SoPC) technology. The acquisition station hardware includes an analog board and a main control board. The analog board uses a signal conditioning circuit and a 24-bit analog-to-digital converter (ADS1271) to achieve high-precision data acquisition, while the main control board uses a low-power SoPC chip to enable high-speed stable data transmission. Moreover, the data transmission protocol for the acquisition station was designed, an improved low-voltage differential signaling data transmission technology was independently developed, and a method to enhance the precision of synchronous acquisition was studied in depth. These key technologies, which were developed for the acquisition station, were integrated into the SoPC of the main control board. Testing results indicate that the synchronization precision of the acquisition station is better than 200 ns, and the maximum low-power data transmission speed is 16 Mbps along a 55 m cable. Simultaneously, the developed acquisition station has the advantages of low noise, large dynamic range, low power consumption, etc., and it can achieve high-precision hybrid acquisition of seismic-electrical data.

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A 4-M Pixel High Dynamic Range, Low-Noise CMOS Image Sensor With Low-Power Counting ADC

IEEE Transactions on Electron Devices ◽

10.1109/ted.2017.2702624 ◽

2017 ◽

Vol 64 (8) ◽

pp. 3199-3205 ◽

Cited By ~ 11

Author(s):

Cheng Ma ◽

Yang Liu ◽

Yang Li ◽

Quan Zhou ◽

Xinyang Wang ◽

...

Keyword(s):

Low Power ◽

Dynamic Range ◽

High Dynamic Range ◽

Cmos Image Sensor ◽

Image Sensor ◽

Low Noise ◽

Power Counting ◽

High Dynamic

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Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling $\Sigma\Delta$ Analog-to-Digital Conversion

IEEE Sensors Journal ◽

10.1109/jsen.2011.2158818 ◽

2012 ◽

Vol 12 (4) ◽

pp. 737-746 ◽

Cited By ~ 24

Author(s):

Zeljko Ignjatovic ◽

Danijel Maricic ◽

Mark F. Bocko

Keyword(s):

Low Power ◽

Dynamic Range ◽

High Dynamic Range ◽

Cmos Image Sensor ◽

Image Sensor ◽

Digital Conversion ◽

Sigma Delta ◽

Analog To Digital ◽

Analog To Digital Conversion ◽

High Dynamic

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Development of a new distributed hybrid seismic and electrical data acquisition station based on system-on-a-programmable-chip technology

Geoscientific Instrumentation Methods and Data Systems ◽

10.5194/gi-8-241-2019 ◽

2019 ◽

Vol 8 (2) ◽

pp. 241-249 ◽

Cited By ~ 4

Author(s):

Qisheng Zhang ◽

Wenhao Li ◽

Feng Guo ◽

Zhenzhong Yuan ◽

Shuaiqing Qiao ◽

...

Keyword(s):

Low Power ◽

Data Acquisition ◽

High Precision ◽

Data Transmission ◽

Dynamic Range ◽

Low Voltage ◽

Low Noise ◽

Transmission Protocol ◽

Control Board ◽

Electrical Data

Abstract. In the past few decades, with the continuous advancement of technology, seismic and electrical instruments have developed rapidly. However, complex and harsh exploration environments led to higher requirements and severe challenges for traditional geophysical exploration methods and instruments. Therefore, it is extremely urgent to develop new high-precision exploration instruments and data acquisition systems. In this study, a new distributed seismic and electrical hybrid acquisition station is developed using system-on-a-programmable-chip (SoPC) technology. The acquisition station hardware includes an analog board and a main control board. The analog board uses a signal conditioning circuit and a 24-bit analog-to-digital converter (ADS1271) to achieve high-precision data acquisition, while the main control board uses a low-power SoPC to enable high-speed stable data transmission. We designed the data transmission protocol for the acquisition station and developed independently an improved low-voltage differential signaling data transmission technology. What's more, a method to enhance the precision of synchronous acquisition was studied in depth. These key technologies, which were developed for the acquisition station, were integrated into the SoPC of the main control board. Test results indicate that the synchronization precision of the acquisition station is better than 200 ns, and the maximum low-power data transmission speed is 16 Mbps along a 55 m cable. The developed acquisition station has the advantages of low noise, large dynamic range, low power consumption, etc., and it can achieve high-precision hybrid acquisition of seismic and electrical data.

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Analog Circuit of Light Detector for CMOS Image Sensor

Optoelectronics in Machine Vision-Based Theories and Applications - Advances in Computational Intelligence and Robotics ◽

10.4018/978-1-5225-5751-7.ch002 ◽

2019 ◽

pp. 17-48

Author(s):

Arjuna Marzuki ◽

Mohd Tafir Mustaffa ◽

Norlaili Mohd. Noh ◽

Basir Saibon

Keyword(s):

Low Power ◽

Analog Circuit ◽

Flicker Noise ◽

Cmos Image Sensor ◽

High Gain ◽

Image Sensor ◽

Low Noise ◽

Plant Phenotyping ◽

Cmos Sensor ◽

Cmos Amplifier

Plant phenotyping studies represent a challenge in agriculture application. The studies normally employ CMOS optical and image sensor. One of the most difficult challenges in designing the CMOS sensor is the need to achieve good sensitivity while achieving low noise and low power simultaneously for the sensor. At low power, the CMOS amplifier in the sensor is normally having a lower gain, and it becomes even worse when the frequency of the interest is in the vicinity of flicker noise region. Using conventional topology such as folded cascode will result in the CMOS amplifier having high gain, but with the drawback of high power. Hence, there is a need for a new approach that improves the sensitivity of the CMOS sensor while achieving low power. The objective of this chapter is to update CMOS sensors and to introduce a modified light integrating circuit which is suitable for CMOS image sensor.

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Amorphous Silicon Image Sensor Arrays

MRS Proceedings ◽

10.1557/proc-258-1127 ◽

1992 ◽

Vol 258 ◽

Cited By ~ 42

Author(s):

M J Powell ◽

I D French ◽

J R Hughes ◽

N C Bird ◽

O S Davies ◽

...

Keyword(s):

Amorphous Silicon ◽

High Speed ◽

Dynamic Range ◽

Sensor Arrays ◽

Image Sensor ◽

Low Noise ◽

Image Sensors ◽

Frame Rate ◽

Intimate Contact ◽

Current Densities

ABSTRACTWe have developed a technology for 2D matrix-addressed image sensors using amorphous silicon photodiodes and thin film transistors. We have built a small prototype, having 192×192 pixels with a 20μm pixel pitch, and assessed its performance. The nip photodiodes can have dark current densities of less than 1011 A.cm-2 (up to 5V reverse bias) and peak quantum efficiencies of 88% (at 580nm). We operated the sensor in real time mode at high speed (50 Hz frame rate and 64μS line time). The image sensor has a low noise performance giving a dynamic range in excess of 104. The maximum crosstalk is about 2%, which allows at least 50 grey levels. The bottom contact of the photodiode acts as a light shield from light through the substrate, which enables the sensor to be operated as an intimate contact image sensor to image a document placed directly on top of the array. In this mode, the CTF was 75% at 2 lp.mm1. Good quality images are demonstrated in both front projection and intimate contact imaging modes.

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A 1.1V 12μW 86dB DR Sigma-Delta Modulator for Health Monitoring System

Journal of Circuits System and Computers ◽

10.1142/s0218126616500596 ◽

2016 ◽

Vol 25 (06) ◽

pp. 1650059

Author(s):

Long Zhao ◽

Chenxi Deng ◽

Guan Wang ◽

Hongming Chen ◽

Yuhua Cheng

Keyword(s):

Power Consumption ◽

Low Power ◽

Monitoring System ◽

Health Monitoring ◽

Dynamic Range ◽

Low Voltage ◽

Supply Voltage ◽

Sigma Delta Modulator ◽

Sigma Delta ◽

Health Monitoring System

A low-voltage low-power Sigma-Delta modulator for health monitoring system is designed using a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. To achieve high accuracy with low power consumption in low supply voltage environment, the designed modulator is implemented with a one-bit third-order topology, in which the input-feedforward structure and switched-opamp (SO) technique are combined. Using the proposed design method, the SO meets the system requirements with the minimal power consumption and good stability in a feedback loop. The modulator achieves 86[Formula: see text]dB dynamic range (DR) over a 300[Formula: see text]Hz bandwidth with an oversampling ratio (OSR) of 128, while it occupies 0.16[Formula: see text]mm2 and consumes 12[Formula: see text][Formula: see text]W under a 1.1[Formula: see text]V supply.

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A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126618501049 ◽

2018 ◽

Vol 27 (07) ◽

pp. 1850104 ◽

Cited By ~ 2

Author(s):

Yuwadee Sundarasaradula ◽

Apinunt Thanachayanont

Keyword(s):

Low Power ◽

Biomedical Applications ◽

Dynamic Range ◽

Supply Voltage ◽

Low Noise ◽

Power Supply Voltage ◽

Wide Dynamic Range ◽

Dc Offset ◽

Limiting Amplifier ◽

Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

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A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

SN Applied Sciences ◽

10.1007/s42452-021-04402-0 ◽

2021 ◽

Vol 3 (4) ◽

Author(s):

S. Chrisben Gladson ◽

Adith Hari Narayana ◽

V. Thenmozhi ◽

M. Bhaskar

Keyword(s):

Low Power ◽

Ieee 802.15.4 ◽

Low Voltage ◽

Low Noise ◽

Low Noise Amplifier ◽

Cmos Process ◽

Process Technology ◽

Ultra Low Power ◽

Power Mode ◽

Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

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