Analog Circuit of Light Detector for CMOS Image Sensor

2019 ◽  
pp. 17-48
Author(s):  
Arjuna Marzuki ◽  
Mohd Tafir Mustaffa ◽  
Norlaili Mohd. Noh ◽  
Basir Saibon
Keyword(s):  
Low Power ◽  
Analog Circuit ◽  
Flicker Noise ◽  
Cmos Image Sensor ◽  
High Gain ◽  
Image Sensor ◽  
Low Noise ◽  
Plant Phenotyping ◽  
Cmos Sensor ◽  
Cmos Amplifier

Plant phenotyping studies represent a challenge in agriculture application. The studies normally employ CMOS optical and image sensor. One of the most difficult challenges in designing the CMOS sensor is the need to achieve good sensitivity while achieving low noise and low power simultaneously for the sensor. At low power, the CMOS amplifier in the sensor is normally having a lower gain, and it becomes even worse when the frequency of the interest is in the vicinity of flicker noise region. Using conventional topology such as folded cascode will result in the CMOS amplifier having high gain, but with the drawback of high power. Hence, there is a need for a new approach that improves the sensitivity of the CMOS sensor while achieving low power. The objective of this chapter is to update CMOS sensors and to introduce a modified light integrating circuit which is suitable for CMOS image sensor.

A 4-M Pixel High Dynamic Range, Low-Noise CMOS Image Sensor With Low-Power Counting ADC

2017 ◽  
Vol 64 (8) ◽  
pp. 3199-3205 ◽  
Author(s):  
Cheng Ma ◽  
Yang Liu ◽  
Yang Li ◽  
Quan Zhou ◽  
Xinyang Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Low Noise ◽  
Power Counting ◽  
High Dynamic

scholarly journals Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1936
Author(s):  
Luis Miguel Carvalho Freitas ◽  
Fernando Morgado-Dias
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Flicker Noise ◽  
Image Sensor ◽  
Low Noise ◽  
Image Noise ◽  
Frame Rate ◽  
Direct Role ◽  
Sigma Delta

Modern CMOS imaging devices are present everywhere, in the form of line, area and depth scanners. These image devices can be used in the automotive field, in industrial applications, in the consumer’s market, and in various medical and scientific areas. Particularly in industrial and scientific applications, the low-light noise performance or the high dynamic-range features are often the cases of interest, combined with low power dissipation and high frame rates. In this sense, the noise floor performance and the power consumption are the focus of this work, given that both are interlinked and play a direct role in the remaining sensor features. It is known that thermal and flicker noise sources are the main contributors to the degradation of the sensor performance, concerning the sensor output image noise. This paper presents an indirect way to reduce both the thermal and the flicker noise contributions by using thin-oxide low voltage supply column readout circuits and fast 3rd order incremental sigma-delta converters with noise shaping capabilities (to provide low noise output digital samples—74 μVrms; 0.7 e−rms; at 105 μV/e−), and thus performing correlated double sampling in a short time (19 μs), while dissipating significant low power (346 μW). Throughout the extensive parametric transistor-level simulations, the readout path produced 1.2% non-linearity, with a competitive saturation capacity (6.5 ke−) pixel. In addition, this paper addresses the readout parallelism as the main point of interest, decoupling resolution from the image noise and the frame rate, at virtually any array resolution. The design and simulations were performed with Virtuoso 6.17 tools (Cadence Design Systems, San Jose, CA, USA) using Spectre models from TS18IS Image Sensor 0.18 µm Process Development Kit (Tower Jazz Semiconductor, Migdal Haemek, Israel).

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

A Two-Tap Indirect Time-of-Flight CMOS Image Sensor With Pump Gate Modulator for Low-Power Applications

2021 ◽  
pp. 1-7
Author(s):  
Bing Zhang ◽  
Congzhen Hu ◽  
Junhua Lai ◽  
Youze Xin ◽  
Zhuoqi Guo ◽  
...  
Keyword(s):  
Low Power ◽  
Time Of Flight ◽  
Cmos Image Sensor ◽  
Image Sensor

scholarly journals Block-Based Low-Power CMOS Image Sensor with a Simple Pixel Structure

2014 ◽  
Vol 23 (2) ◽  
pp. 87-93
Author(s):  
Ju-Yeong Kim ◽  
Jeongyeob Kim ◽  
Myunghan Bae ◽  
Sung-Hyun Jo ◽  
Minho Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Low Power Cmos ◽  
Block Based
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