scholarly journals A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2494
Author(s):  
Lu Tang ◽  
Kuidong Chen ◽  
Youming Zhang ◽  
Xusheng Tang ◽  
Changchun Zhang
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Frequency Divider ◽  
Flip Flop ◽  
Ka Band ◽  
Locking Range ◽  
Type Frequency ◽  
Operation Frequency ◽  
Programmable Frequency Divider

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

The Design of a 5 GHz Programmable Frequency Divider for Fractional-N Frequency Synthesizer

2011 ◽  
Vol 341-342 ◽  
pp. 623-628
Author(s):  
Zhong Shan Chen ◽  
Yan Tu ◽  
Liang Feng
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Critical Path ◽  
Propagation Delay ◽  
Frequency Divider ◽  
Cmos Process ◽  
5 Ghz ◽  
Work Up ◽  
Timing Requirement ◽  
Programmable Frequency Divider

The design of a high speed programmable frequency divider for fractional-N frequency synthesizer is presented. The programmable divider consists of a divide-by-4/5 dual-modulus prescaler, a 5-bit programmable counter, and a 2-bit swallow counter. A new scheme of reload operation is adopted to reduce the propagation delay of the critical path. The triggering signal for the two counters is selected carefully to mitigate the timing requirement of the mode control signal. The divider is designed in 0.18 um CMOS process. Its division ratio (DR) covers the range from 12 to 127. Post-layout simulations show it can work up to 5 GHz under 1.8 V power supply, while consuming only 9 mW and occupying an area of about 0.06 mm2.

A Programmable Frequency Divider for Multi-Standard Wireless Receivers

2014 ◽  
Vol 577 ◽  
pp. 644-647 ◽  
Author(s):  
Jia Feng Wang ◽  
Xiang Ning Fan ◽  
Li Tang ◽  
Xiao Yang Shi
Keyword(s):  
Mobile Communications ◽  
Short Distance ◽  
High Speed ◽  
Frequency Synthesizer ◽  
Frequency Divider ◽  
Wireless Receivers ◽  
Circuit Structure ◽  
Distance Communication ◽  
Simulation Results ◽  
Programmable Frequency Divider

A programmable frequency divider based on divider-by-2/3 structure in fractional-N frequency synthesizer is presented, including a high speed divider-by-2 providing orthogonal signals for mixer. This paper firstly introduces two structures of programmable frequency divider, and analyzes the rationality of the circuit structure. Then it presents a method to determine the parameters of CMOS transistors in SCL structure. Finally, each component of the circuit is analyzed. The simulation results show that the programmable divider can work at 1 ~ 8 GHz and generates programmable division ratio from 32 to 127. This programmable frequency divider can be used in mobile communications, satellite navigation, short distance communication and other systems.

A Ka-band wide locking range frequency divider with high injection sensitivity

2014 ◽  
Vol 35 (3) ◽  
pp. 035002 ◽  
Author(s):  
Faen Liu ◽  
Zhigong Wang ◽  
Zhiqun Li ◽  
Qin Li ◽  
Lu Tang ◽  
...  
Keyword(s):  
Frequency Divider ◽  
Ka Band ◽  
Locking Range ◽  
High Injection ◽  
Wide Locking Range

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

A 36 GHz CIFF-TFF Dynamic Frequency Divider Using GaAs HBTs

2013 ◽  
Vol 441 ◽  
pp. 125-128
Author(s):  
Li Fan Wu
Keyword(s):  
High Speed ◽  
Heterojunction Bipolar Transistor ◽  
Frequency Divider ◽  
Schematic Diagram ◽  
60 Ghz ◽  
Flip Flop ◽  
Simulation Methodology ◽  
The Core ◽  
Core Part ◽  
Dynamic Frequency

A clock-inverter feed-forward toggle flip-flop (CIFF-TFF) based ultra-high-speed 2:1 dynamic frequency divider is designed in a GaAs heterojunction bipolar transistor (HBT) technology with fT of 60 GHz from Win Semiconductors corporation. The co-simulation methodology of electromagnetic field and schematic diagram is utilized in the design. Through tuning the currents in the core and the other parts of the divider separately, the dynamic frequency divider approaches an operating speed of 36 GHz with a power consumption of 162 mW in the core part from a single 6 V supply. The design is currently taped out.

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