A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

2022 ◽  
Vol 43 (1) ◽  
pp. 012401
Author(s):  
Quan Pan ◽  
Xiongshi Luo
Keyword(s):  
Optical Measurement ◽  
Supply Voltage ◽  
Electrical Measurement ◽  
High Gain ◽  
Input Device ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Bandwidth Enhancement ◽  
Inductive Peaking ◽  
Capacitive Loading

Abstract This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, input series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device, achieving an overall bandwidth enhancement ratio of 8.5. The electrical measurement shows TIA achieves 58 dBΩ up to 12.7 GHz with a 180-fF off-chip photodetector. The optical measurement demonstrates a clear open eye of 20 Gb/s. The TIA dissipates 4 mW from a 1.2-V supply voltage.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

A MULTI-BAND LOW NOISE AMPLIFIER WITH GAIN FLATNESS AND BANDWIDTH ENHANCEMENT

2014 ◽  
Vol 23 (02) ◽  
pp. 1450017 ◽  
Author(s):  
SAN-FU WANG ◽  
JAN-OU WU ◽  
YANG-HSIN FAN ◽  
JHEN-JI WANG
Keyword(s):  
Performance Enhancement ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Bandwidth Enhancement ◽  
Input Matching ◽  
Noise Amplifier ◽  
Tunable Frequency ◽  
Multi Band

In this paper, a differential multi-band CMOS low noise amplifier (LNA) is proposed that is operated within a range of 1500–2700 MHz with input matching capacitor switching and gain flatness performance enhancement technique. Traditional multi-band LNAs have poor performances on gain flatness performance. Therefore, we propose a new multi-band LNA which obtain good gain flatness performance by integrating the characteristics of the transistor trans-conductance and LC resonant load. The new LNA can also achieve a tunable frequency at different matching capacitance conditions. The post-layout simulation results shows that the voltage gain is between 19.3 dB and 22.4 dB, the NF is less than 2.5 dB, and the 1-dB compression point is about -5.1 dBm. The LNA consumes 17.79 mW under 1.8 V supply voltage in TSMC 0.18-um RF CMOS process.

π-PEAKING SHUNT-FEEDBACK TRANSIMPEDANCE AMPLIFIER WITH BANDWIDTH ENHANCEMENT

2013 ◽  
Vol 22 (09) ◽  
pp. 1340009
Author(s):  
PANUS SINSOONTORNPONG ◽  
APISAK WORAPISHET
Keyword(s):  
Circuit Complexity ◽  
High Gain ◽  
Low Noise ◽  
Transimpedance Amplifier ◽  
Noise Performance ◽  
Bandwidth Enhancement ◽  
High Bandwidth ◽  
Practical Performance ◽  
Cmos Implementation ◽  
Silicon Cmos

This paper presents the development of a bandwidth enhancement technique for a resistive shunt-feedback transimpedance amplifier (TIA). The technique relies upon a π-peaking network realization using the shunt-feedback TIA as a part of the network in order to achieve a high bandwidth while maintaining a low noise performance. The output is obtained by making use of subsequent amplifier stages with the non-uniform constant-k output network for simultaneously high gain and bandwidth. Practical performance verification was provided via the designs and simulations of two π-peaking TIAs in a silicon CMOS implementation and a discrete HJFET implementation. Simulated results clearly indicates superior bandwidth of the π-peaking TIA over the conventional shunt-feedback TIA at practically no cost to circuit complexity and power consumption.

A High Gain, 808MHz GBW Four-Stage OTA in 65nm CMOS

2019 ◽  
Vol 28 (11) ◽  
pp. 1950192
Author(s):  
Zhe Li ◽  
Rui Ma ◽  
Maliang Liu ◽  
Ruixue Ding ◽  
Zhangming Zhu
Keyword(s):  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Model Stability ◽  
Analysis And Design ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Compensation Technique ◽  
Layout Area ◽  
The Stability

A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath [Formula: see text]-[Formula: see text] compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65[Formula: see text]nm 1.2[Formula: see text]V CMOS process, achieving 808[Formula: see text]MHz gain-bandwidth, 119[Formula: see text]dB DC gain, 585[Formula: see text]V/[Formula: see text]s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2[Formula: see text]V with power consumption of 2.17[Formula: see text]mW and the layout area is 0.011[Formula: see text]mm2.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

scholarly journals Ultra compact multi-standard low-noise amplifiers in 28 nm CMOS with inductive peaking

2017 ◽  
Vol 10 (1) ◽  
pp. 47-57
Author(s):  
Elena Sobotta ◽  
Guido Belfiore ◽  
Frank Ellinger
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Bandwidth Enhancement ◽  
Dc Power ◽  
Active Inductors ◽  
Inductive Peaking ◽  
Noise Amplifier ◽  
28 Nm

This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the gm/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Ku band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than −12 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm2, whereas the version with vertical inductors requires 0.021 mm2.

scholarly journals A 4 GHz Single-to-Differential Cross-Coupled Variable-Gain Transimpedance Amplifier for Optical Communication

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3042
Author(s):  
Samuel B. S. Lee ◽  
Kiat Seng Yeo
Keyword(s):  
Optical Communication ◽  
Dynamic Range ◽  
Visible Light Communication ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Bandwidth Enhancement ◽  
Variable Gain ◽  
Noise Current ◽  
Dc Power ◽  
Capacitive Load

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified fT-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/Hz, core DC power consumption is 7.84 mW from a VDDTIA of 1.6 V and core area is 39 µm × 26 µm.

Design of Wide Bandwidth, High-CMRR Voltage and Transadmittance-Mode Instrumentation Amplifier Using a Single CBTA

2019 ◽  
Vol 29 (04) ◽  
pp. 2050060
Author(s):  
Mehmet Sagbas ◽  
Umut Engin Ayten
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
High Gain ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Wide Bandwidth ◽  
Current Output ◽  
Transconductance Amplifier ◽  
Low Offset ◽  
Electronically Tunable

In this work, a high-performance voltage and current output instrumentation amplifier circuit is proposed. The proposed circuit also has voltage-mode (VM) and transadmittance-mode (TAM) outputs at a time. It employs a single current backward transconductance amplifier (CBTA) and a grounded resistor. It has the advantage of having low input and high output impedances which makes it easy for cascadability. The presented circuit has electronically tunable property due to the bias current of the CBTA. The validity of the proposed circuit is demonstrated by PSPICE simulations using a 0.18[Formula: see text][Formula: see text]m CMOS process with [Formula: see text][Formula: see text]V supply voltage. Simulation results show that the proposed circuit has a high common mode rejection ratio (CMRR), wide bandwidth, low offset and high gain properties.

A 100-MS/s CMOS Sample-and-Hold Circuit with Input Common Mode Feedback

2013 ◽  
Vol 748 ◽  
pp. 847-852
Author(s):  
Jun Yang ◽  
Hong Hui Deng ◽  
Rui Zhang ◽  
Yong Sheng Yin
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sample And Hold ◽  
Feedback Capacitor

A high performance sample-and-hold (S/H) circuit with input common mode feedback (ICMFB) is presented. The ICMFB is used to ensure that the input common mode voltage for the sample-and-hold amplifier (SHA) is maintained at a known value during the hold phase of operation in order to reduce the differential output error when the sample capacitor and feedback capacitor has mismatch. Meanwhile, bootstrapped switches are used to lower the switch on-resistance and reduce the effect of switch non-idealities. Then a low power two stage high gain wideband SHA is designed to guarantee the holding accuracy. Hspice simulated results based on SMIC 0.13μm 1P5M CMOS process under 1.2V supply voltage shows a 108.4 dB spurious free dynamic range (SFDR) at Nyquist input @Fs=100MS/s. The designed S/H circuit has been used in the front end of 14-bit 100MS/s Pipelined ADC adapted for single-ended applications.

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