Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects

2020 ◽  
Vol 29 (12) ◽  
pp. 2050185 ◽  
Author(s):  
Himanshu Sharma ◽  
Karmjit Singh Sandha
Keyword(s):  
Integrated Circuit ◽  
Fermi Energy ◽  
Large Scale ◽  
Graphene Nanoribbons ◽  
Layer Graphene ◽  
Parasitic Parameters ◽  
On Chip ◽  
Power Delay Product ◽  
Technology Nodes ◽  
The Impact

Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.

CNT as Interconnects

2020 ◽  
pp. 130-159
Author(s):  
Karmjit Singh Sandha
Keyword(s):  
Comparative Analysis ◽  
Equivalent Circuit ◽  
Integrated Circuit ◽  
Equivalent Circuit Model ◽  
Global Level ◽  
Electrical Equivalent Circuit ◽  
Swcnt Bundle ◽  
Impedance Parameters ◽  
Power Delay Product ◽  
Technology Nodes

The chapter will start with brief introduction to the interconnects and its importance in an integrated circuit at deep sub-micron technology nodes. The brief discussion about the concept of scaling, interconnects models, and material in use are presented. The limitations of conventional materials at scaled down technology nodes will be discussed next. The focus of the chapter is to present the electrical equivalent circuit model to estimate the impedance parameters of SWCNT bundle and MWCNT bundle as interconnects at different nano-scaled technology nodes for global level interconnect length. Using ESC model of SWCNT, MWCNT, and copper, the performance comparative analysis for delay and power delay product (PDP) will be presented for different interconnect lengths at nano-scaled technology nodes. Finally, the chapter summary and conclusion will be written at the end of the chapter.

scholarly journals Organic printed photonics: From microring lasers to integrated circuits

2015 ◽  
Vol 1 (8) ◽  
pp. e1500257 ◽  
Author(s):  
Chuang Zhang ◽  
Chang-Ling Zou ◽  
Yan Zhao ◽  
Chun-Hua Dong ◽  
Cong Wei ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flexible Electronics ◽  
Integrated Circuit ◽  
Large Scale ◽  
Rapid Development ◽  
Light Signal ◽  
Photonic Integrated Circuit ◽  
Printing Technique ◽  
On Chip ◽  
Silicon Based

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

scholarly journals DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 122
Author(s):  
Jiemin Li ◽  
Shancong Zhang ◽  
Chong Bao
Keyword(s):  
Error Detection ◽  
Integrated Circuit ◽  
Large Scale ◽  
Fault Tolerant ◽  
Soft Errors ◽  
Implementation Process ◽  
Radiation Environment ◽  
Cmos Integrated Circuit ◽  
Processor Core ◽  
The Impact

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes

2021 ◽  
Author(s):  
Gurleen Dhillon ◽  
Karmjit Singh Sandha
Keyword(s):  
Carbon Nanotube ◽  
Integrated Circuit ◽  
Promising Result ◽  
Propagation Delay ◽  
Multi Walled Carbon Nanotube ◽  
The Stability ◽  
Power Delay Product ◽  
Dissipation Power ◽  
Technology Nodes ◽  
Transmission Line Models

The temperature-dependent modeling technique (in the temperature range of 200–500[Formula: see text]K) for a mixed class of carbon nanotube (CNT) bundle interconnects is proposed. The equivalent single conductor (ESC) transmission line models of multi-walled carbon nanotube (MWCNT) and double-walled carbon nanotube (DWCNT) are combined to develop multiple single conductor (MSC) model of mixed CNT interconnects. Various possible arrangements of densely packed MWCNT and DWCNT bundles (MDCB) are considered to form different types of mixed CNT bundle structures (MDCB-1, MDCB-2, MDCB-3 and MDCB-4). The integrated circuit emphasis simulation is performed and the performances of these mixed CNT bundle interconnects are investigated in terms of propagation delay (with and without crosstalk), power dissipation, power-delay product (PDP). Switching times, overshoot voltages and Nyquist plots are analyzed to check the stability of these mixed CNT structures for global interconnect length for 32-nm, 22-nm and 16-nm technology nodes. It is observed that the MDCB-1 structure yields the most promising result in all aspects for interconnect applications in the near future.

scholarly journals Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review

2018 ◽  
Vol 4 (3) ◽  
pp. 49 ◽  
Author(s):  
Arnab Hazra ◽  
Sukumar Basu
Keyword(s):  
Large Scale ◽  
Graphene Nanoribbons ◽  
High Current Density ◽  
Graphene Film ◽  
Side Wall ◽  
Graphene Nanoribbon ◽  
Practical Implementation ◽  
High Electron ◽  
On Chip ◽  
Interconnect Material

In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS).

scholarly journals CONTANGO: Integrated Optimization of SoC Clock Networks

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Dong-Jin Lee ◽  
Igor L. Markov
Keyword(s):  
Large Scale ◽  
Analytical Models ◽  
Large Scale Optimization ◽  
Semiconductor Technology ◽  
Clock Networks ◽  
Technology Scaling ◽  
Synchronous Circuits ◽  
On Chip ◽  
Scale Optimization ◽  
Technology Nodes

On-chip clock networks are remarkable in their impact on the performance and power of synchronous circuits, in their susceptibility to adverse effects of semiconductor technology scaling, as well as in their strong potential for improvement through better CAD algorithms and tools. Existing literature is rich in ideas and techniques but performs large-scale optimization using analytical models that lost accuracy at recent technology nodes and have rarely been validated by realistic SPICE simulations on large industry designs. Our work offers a methodology for SPICE-accurate optimization of clock networks, coordinated to satisfy slew constraints and achieve best tradeoffs between skew, insertion delay, power, as well as tolerance to variations. Our implementation, called Contango, is evaluated on 45 nm benchmarks from IBM Research and Texas Instruments with up to 50 K sinks. It outperforms all published results in terms of skew and shows superior scalability.

Impact of Material Properties on Cooling COP of Integrated Thermoelectric Microcoolers

2013 ◽  
Author(s):  
Yee Rui Koh ◽  
Kazuaki Yazawa ◽  
Ali Shakouri
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuit ◽  
Hot Spot ◽  
Coefficient Of Performance ◽  
Total Power ◽  
Vapor Compression ◽  
Total Power Consumption ◽  
On Chip ◽  
The Individual ◽  
The Impact

Thermoelectric (TE) microcooling is promising for removing hotspots in integrated circuit chips. The cooling coefficient-of-performance (COP) of the on-chip thin film or superlattice micro-cooler (SLC) is a metric for assessing the energy efficiency of the hot spot removal. The COP is key for lowering total power consumption and minimizing heat sinking requirements. Due to the moderate performance compared to vapor compression cycles, researchers have devoted considerable effort to improving the figure-of-merit (ZT) of the material over the past decade. However, the impact of each of the individual thermoelectric properties has not been studied separately. We report our study based on an analytical model and analysis results that show the intrinsic impact of electrical conductivity, the Seebeck coefficient, and thermal conductivity, while the device thickness and the drive current are optimized for maximizing cooling COP. The results show that the power factor of the TE materials is a more important parameter than thermal conductivity reduction for improving the cooling performance of the on chip SLC.

scholarly journals An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

2012 ◽  
Vol 2012 ◽  
pp. 1-15 ◽  
Author(s):  
Andrew G. Schmidt ◽  
William V. Kritikos ◽  
Shanyuan Gao ◽  
Ron Sass
Keyword(s):  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
Large Scale ◽  
The Body ◽  
And Performance ◽  
On Chip ◽  
Point To Point ◽  
Computing Machines ◽  
Performance Computing

As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster. The system supports MPI-style point-to-point messages, collectives, and other novel communication. Results include the resource utilization and performance (in latency and bandwidth).

Impact of COVID-19 on Nuclear Medicine in Germany, Austria and Switzerland: An International Survey in April 2020

2020 ◽  
Vol 59 (04) ◽  
pp. 294-299 ◽  
Author(s):  
Lutz S. Freudenberg ◽  
Ulf Dittmer ◽  
Ken Herrmann
Keyword(s):  
Nuclear Medicine ◽  
Health Systems ◽  
Personal Protective Equipment ◽  
Large Scale ◽  
Diagnostic Procedures ◽  
Protective Equipment ◽  
Current Crisis ◽  
Web Based ◽  
Public Versus Private ◽  
The Impact

Abstract Introduction Preparations of health systems to accommodate large number of severely ill COVID-19 patients in March/April 2020 has a significant impact on nuclear medicine departments. Materials and Methods A web-based questionnaire was designed to differentiate the impact of the pandemic on inpatient and outpatient nuclear medicine operations and on public versus private health systems, respectively. Questions were addressing the following issues: impact on nuclear medicine diagnostics and therapy, use of recommendations, personal protective equipment, and organizational adaptations. The survey was available for 6 days and closed on April 20, 2020. Results 113 complete responses were recorded. Nearly all participants (97 %) report a decline of nuclear medicine diagnostic procedures. The mean reduction in the last three weeks for PET/CT, scintigraphies of bone, myocardium, lung thyroid, sentinel lymph-node are –14.4 %, –47.2 %, –47.5 %, –40.7 %, –58.4 %, and –25.2 % respectively. Furthermore, 76 % of the participants report a reduction in therapies especially for benign thyroid disease (-41.8 %) and radiosynoviorthesis (–53.8 %) while tumor therapies remained mainly stable. 48 % of the participants report a shortage of personal protective equipment. Conclusions Nuclear medicine services are notably reduced 3 weeks after the SARS-CoV-2 pandemic reached Germany, Austria and Switzerland on a large scale. We must be aware that the current crisis will also have a significant economic impact on the healthcare system. As the survey cannot adapt to daily dynamic changes in priorities, it serves as a first snapshot requiring follow-up studies and comparisons with other countries and regions.

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