scholarly journals A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 132 ◽  
Author(s):  
Hongda Zhang ◽  
Peiyuan Wan ◽  
Jiarong Geng ◽  
Zhaozhe Liu ◽  
Zhijie Chen
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Supply Voltage ◽  
Clock Cycle ◽  
Response Speed ◽  
Drop Out ◽  
Cmos Process ◽  
Fast Transient Response ◽  
Signal Converter ◽  
Low Supply Voltage

The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

scholarly journals A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1668
Author(s):  
Shengping Lv ◽  
Peiyuan Wan ◽  
Hongda Zhang ◽  
Jiarong Geng ◽  
Jiabao Wen ◽  
...  
Keyword(s):  
Response Time ◽  
Transient Response ◽  
Output Voltage ◽  
Clock Cycle ◽  
Response Speed ◽  
Drop Out ◽  
Cmos Process ◽  
Error Detector ◽  
Current Steps ◽  
Ldo Regulator

Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at VOUT = 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF.

scholarly journals A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

2021 ◽  
Vol 16 ◽  
pp. 262-274
Author(s):  
Said El Mouzouade ◽  
Karim El Khadiri ◽  
Zakia Lakhliai ◽  
Driss Chenouni ◽  
Ahmed Tahiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Drop Out ◽  
Voltage Regulator ◽  
Hybrid Mode ◽  
Fast Transient Response ◽  
Iot Applications ◽  
Response Performance ◽  
Fast Transient ◽  
Ldo Regulator

A hybrid-mode low-drop out (LDO) voltage regulator with fast transient response performance for IoT applications is proposed in this paper. The proposed LDO regulator consist of two sections. First section is an analog regulator which includes a folded cascode operational amplifier to achieve good PSRR. Second section is current DAC and detectors whitch includes a cource current DAC, sink current DAC, undershoot detectors, and overshoot detectors. The current DAC and detectors are designed to obtain a low drop out and fast transient response. The proposed hybrid-mode LDO voltage regulator has been designed, simulated and layouted in Cadence using TSMC 90 nm CMOS technology. The input range of the LDO regulator is 1.2–2.0 V, and it can produces an output voltage of 1.2V. The LDO regulator achieves 58uA quiescent current, -69 PSRR @ 1 KHz noise frequency and an output voltage drop of around 60mV for a load current step of 100 mA. The final design occupies approximately 0.09 mm2.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2017 ◽  
Vol 26 (12) ◽  
pp. 1750197 ◽  
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Load Current ◽  
Rate Enhancement ◽  
Error Amplifier ◽  
Response Enhancement

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.

A HIGH EFFICIENCY ADAPTIVE CURRENT MODE STEP-UP/STEP-DOWN DC–DC CONVERTER WITH FOUR MODES FOR SMOOTH TRANSITION

2014 ◽  
Vol 23 (07) ◽  
pp. 1450097 ◽  
Author(s):  
YANZHAO MA ◽  
SHAOXI WANG ◽  
SHENGBING ZHANG ◽  
XIAOYA FAN
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
High Efficiency ◽  
Current Mode ◽  
Smooth Transition ◽  
Maximum Efficiency ◽  
Cmos Process ◽  
Voltage Ripple ◽  
Transition Modes ◽  
Step Down

This paper presents a current mode step-up/step-down DC–DC converter with high efficiency, small output voltage ripple, and fast transient response. The control scheme adaptively configures the converter into the proper operation mode. The efficiency is improved by reducing the switching loss, wherein the converter operates like a buck or boost converter, and conduction loss, wherein the average inductor current is reduced in transition modes. The output voltage ripple is significantly reduced by incorporating two constant time transition modes. A fast line transient response is achieved with small overshoot and undershoot voltage. An adaptive substrate selector (ASS) is introduced to dynamically switch the substrate of PMOS power transistors to the highest on-chip voltage. A lossless self-biased current sensor with high-speed and high-accuracy is also achieved. The proposed converter was designed with a standard 0.5 μm CMOS process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V. The maximum load current is 600 mA, and the maximum efficiency is 94%. The output voltage ripple is less than 15 mV in all operation modes.

scholarly journals A low quiescent current low dropout voltage regulator with self-compensation

2019 ◽  
Vol 8 (1) ◽  
pp. 65-73
Author(s):  
Chu-Liang Lee ◽  
Roslina Mohd Sidek ◽  
Nasri Sulaiman ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Supply Voltage ◽  
Drop Out ◽  
Voltage Regulator ◽  
Cmos Process ◽  
Process Technology ◽  
Worst Case ◽  
Unity Gain ◽  
Quiescent Current ◽  
Additional Current ◽  
Loop Stability

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.

Performance of Interconnection and Damping Assignment Passivity-Based Controller on Inverter Circuits

2017 ◽  
Vol 8 (1) ◽  
pp. 69
Author(s):  
N. H. Ramlan ◽  
N. A. Azli ◽  
N. F. A. A. Hafidz
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Harmonic Distortion ◽  
Load Condition ◽  
Voltage Regulation ◽  
Fast Transient Response ◽  
Hamiltonian Theory ◽  
Extension Work ◽  
Low Levels ◽  
Averaged Model

This paper presents an extension work on the application of interconnection and damping assignment passivity-based controller (IDA-PBC) from the conventional H-bridge inverter to a 5-level Cascaded H-bridge Multilevel Inverter (CHMI). With the controller, the inductor current and the voltage capacitor track the desired reference of the inverter to ensure that the output voltage maintains its regulation while the Total Harmonic Distortion (THD) is kept at low levels with fast transient response. It is designed based on the Port-Control Hamiltonian theory exploiting the dissipation properties of the averaged model of inverter circuits.  The results obtained have proven that the IDA-PBC previously developed for the H-bridge inverter can be easily extended and applied to the CHMI circuit. The simulation results showed that the IDA-PBC is able to maintain the output voltage regulation in both circuits in the case of no-load to full-load condition, load uncertainty, and structural uncertainty while maintaining THD of less than 5%. However, in all cases, CHMI has shown better performance in terms of THD percentage and transient response compared to the H-bridge inverter, which are 290 µs and 150 µs respectively.

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