Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (VBK) were changed slightly after adding this SJ structure. The VBK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the VBK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.

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Research on ESD Protection of Ultra-high Voltage nLDMOS Devices by Super-junction Engineering in the Drain-side Drift Region

IEEE Journal of the Electron Devices Society ◽

10.1109/jeds.2021.3102278 ◽

2021 ◽

pp. 1-1

Author(s):

Tien-Yu Lan ◽

Shen-Li Chen ◽

Hung-Wei Chen ◽

Yi-Mu Lee

Keyword(s):

High Voltage ◽

Drift Region ◽

Drain Side ◽

Esd Protection ◽

Ultra High Voltage

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Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Electronics ◽

10.3390/electronics9050718 ◽

2020 ◽

Vol 9 (5) ◽

pp. 718

Author(s):

Sheng-Kai Fan ◽

Shen-Li Chen ◽

Po-Lin Lin ◽

Hung-Wei Chen

Keyword(s):

Schottky Diode ◽

High Voltage ◽

Low Voltage ◽

Channel Width ◽

Drift Region ◽

Operating Voltage ◽

Equivalent Series Resistance ◽

Drain Side ◽

Region Length ◽

Latch Up

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

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Merits of designing Tunnel Field Effect Transistors with underlap near drain region

2015 Annual IEEE India Conference (INDICON) ◽

10.1109/indicon.2015.7443560 ◽

2015 ◽

Author(s):

Upasana ◽

Mridula Gupta ◽

Rakhi Narang ◽

Manoj Saxena

Keyword(s):

Field Effect ◽

Field Effect Transistors ◽

Drain Region

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ESD-Immunity Influence of Ultra-high Voltage nLDMOS as the Drift Region Embedded a P-well

2019 IEEE Eurasia Conference on IOT, Communication and Engineering (ECICE) ◽

10.1109/ecice47484.2019.8942662 ◽

2019 ◽

Author(s):

Po-Lin Lin ◽

Shen-Li Chen ◽

Sheng-Kai Fan ◽

Yu-Jie Zhou ◽

Tien-Yu Lan ◽

...

Keyword(s):

High Voltage ◽

Drift Region ◽

Ultra High Voltage

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Evaluation of the Dynamic-Response-Based Intact Stability Criterion for Floating Wind Turbines

Volume 9: Ocean Renewable Energy ◽

10.1115/omae2015-42008 ◽

2015 ◽

Cited By ~ 1

Author(s):

Marco Masciola ◽

Xiaohong Chen ◽

Qing Yu

Keyword(s):

Wind Speed ◽

Dynamic Response ◽

Wind Turbines ◽

Stability Criterion ◽

Area Ratio ◽

Operating Conditions ◽

Dynamic Responses ◽

Stability Criteria ◽

Intact Stability ◽

Overturning Moment

As an alternative to the conventional intact stability criterion for floating offshore structures, known as the area-ratio-based criterion, the dynamic-response-based intact stability criteria was initially developed in the 1980s for column-stabilized drilling units and later extended to the design of floating production installations (FPIs). Both the area-ratio-based and dynamic-response-based intact stability criteria have recently been adopted for floating offshore wind turbines (FOWTs). In the traditional area-ratio-based criterion, the stability calculation is quasi-static in nature, with the contribution from external forces other than steady wind loads and FOWT dynamic responses captured through a safety factor. Furthermore, the peak wind overturning moment of FOWTs may not coincide with the extreme storm wind speed normally prescribed in the area-ratio-based criterion, but rather at the much smaller rated wind speed in the power production mode. With these two factors considered, the dynamic-response-based intact stability criterion is desirable for FOWTs to account for their unique dynamic responses and the impact of various operating conditions. This paper demonstrates the implementation of a FOWT intact stability assessment using the dynamic-response-based criterion. Performance-based criteria require observed behavior or quantifiable metrics as input for the method to be applied. This is demonstrated by defining the governing load cases for two conceptual FOWT semisubmersible designs at two sites. This work introduces benchmarks comparing the area-ratio-based and dynamic-response-based criteria, gaps with current methodologies, and frontier areas related to the wind overturning moment definition.

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Analysis of Capacitance to Ground Formulas for Different High-Voltage Electrodes

Energies ◽

10.3390/en11051090 ◽

2018 ◽

Vol 11 (5) ◽

pp. 1090 ◽

Cited By ~ 1

Author(s):

Jordi-Roger Riba ◽

Francesca Capelli

Keyword(s):

High Voltage ◽

Fem Simulation ◽

Operating Conditions ◽

Power Supplies ◽

Measuring Instruments ◽

Stray Capacitance ◽

Analytical Formulas ◽

Circular Rings ◽

Available Information ◽

Limited Scope

Stray capacitance can seriously affect the behavior of high-voltage devices, including voltage dividers, insulator strings, modular power supplies, or measuring instruments, among others. Therefore its effects must be considered when designing high-voltage projects and tests. Due to the difficulty in measuring the effects of stray capacitance, there is a lack of available experimental data. Therefore, for engineers and researchers there is a need to revise and update the available information, as well as to have useful and reliable data to estimate the stray capacitance in the initial designs. Although there are some analytical formulas to calculate the capacitance of some simple geometries, they have a limited scope. However, since such formulas can deal with different geometries and operating conditions, it is necessary to assess their consistency and applicability. This work calculates the stray capacitance to ground for geometries commonly found in high-voltage laboratories and facilities, including wires or rods of different lengths, spheres and circular rings, the latter ones being commonly applied as corona protections. This is carried out by comparing the results provided by the available analytical formulas with those obtained from finite element method (FEM) simulation, since field simulation methods allow solving such problem. The results of this work prove the suitability and flexibility of the FEM approach, because FEM models can deal with wider range of electrodes, configurations and operating conditions.

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High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

Materials Science Forum ◽

10.4028/www.scientific.net/msf.778-780.841 ◽

2014 ◽

Vol 778-780 ◽

pp. 841-844 ◽

Cited By ~ 1

Author(s):

Koji Nakayama ◽

Shuji Ogata ◽

Toshihiko Hayashi ◽

Tetsuro Hemmi ◽

Atsushi Tanaka ◽

...

Keyword(s):

High Voltage ◽

Recovery Time ◽

Carrier Lifetime ◽

Low Voltage ◽

Reduction Rate ◽

Drift Region ◽

Pin Diode ◽

Fully Depleted ◽

Fast Switching ◽

Reverse Recovery Time

The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.

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