scholarly journals Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power

2018 ◽  
Vol 7 (3.1) ◽  
pp. 27
Author(s):  
Vengadeswari N ◽  
Priscilla Whitin
Keyword(s):  
Supply Voltage ◽  
Charge Pump ◽  
Major Elements ◽  
Leakage Power ◽  
Power Gating ◽  
Charge Pumps ◽  
Pumping Efficiency ◽  
Low Power Cmos ◽  
Two Parameters ◽  
Charge Pump Circuit

In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools. 

scholarly journals Efficiency of Innovative Charge Pump versus Clock Frequency and MOSFETs Sizes

2016 ◽  
Vol 16 (5) ◽  
pp. 260-265 ◽  
Author(s):  
David Matoušek ◽  
Jiří Hospodka ◽  
Ondřej Šubrt
Keyword(s):  
Output Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Specific Power ◽  
Pump Efficiency ◽  
Clock Frequency ◽  
Output Current ◽  
Charge Pumps ◽  
Complex Optimization ◽  
Charge Pump Circuit

Abstract Charge pumps are circuits that produce the voltage higher than supply voltage or negative voltage. Today, charge pumps became an integral part of the electronic equipment. The integration of charge pumps directly into the system allows manufacturers to feed a complex system with many specific power requirements from a single source. However, charge pump efficiency is reduced by many phenomena. This paper is focused on the question of efficiency of proposed variant of the charge pump. In this article, the efficiency dependence on a number of stages, output current, clock frequency and MOSFETs sizes was simulated by Eldo. The aim of this study is to determine the MOSFETs sizes and theirs influence to efficiency and the output voltage. Complex optimization of the charge pump circuit will follow in further text.

scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

2005 ◽  
Vol 14 (05) ◽  
pp. 997-1006 ◽  
Author(s):  
ROBERT C. CHANG ◽  
LUNG-CHIH KUO ◽  
HOU-MING CHEN
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Low Power Cmos ◽  
Charge Pump Circuit ◽  
Frequency Detector

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

scholarly journals Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

2018 ◽  
Vol 8 (6) ◽  
pp. 4120
Author(s):  
Sung Sik Park ◽  
Ju Sang Lee ◽  
Sang Dae Yu
Keyword(s):  
Circuit Simulation ◽  
Pulse Height ◽  
Charge Pump ◽  
Cmos Process ◽  
Charge Pumps ◽  
Current Matching ◽  
Low Jitter ◽  
A New Technique ◽  
Charge Pump Circuit ◽  
Frequency Detector

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.

scholarly journals Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

2019 ◽  
Vol 7 (3) ◽  
pp. 11-18
Author(s):  
Yogesh Kulshethra ◽  
Manish Kule
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Leakage Power ◽  
Power Gating ◽  
Design Constraint ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Look Ahead ◽  
Simulation Results ◽  
Gating Scheme

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

scholarly journals New Discrete Fibonacci Charge Pump Design, Evaluation and Measurement

2017 ◽  
Vol 17 (3) ◽  
pp. 100-107 ◽  
Author(s):  
David Matoušek ◽  
Jiří Hospodka ◽  
Ondřej Šubrt
Keyword(s):  
Printed Circuit Board ◽  
Charge Pump ◽  
Circuit Board ◽  
Design Evaluation ◽  
Clock Frequency ◽  
Pump Design ◽  
Charge Pumps ◽  
Printed Circuit ◽  
Variable Power ◽  
Charge Pump Circuit

AbstractThis paper focuses on the practical aspects of the realisation of Dickson and Fibonacci charge pumps. Standard Dickson charge pump circuit solution and new Fibonacci charge pump implementation are compared. Both charge pumps were designed and then evaluated by LTspice XVII simulations and realised in a discrete form on printed circuit board (PCB). Finally, the key parameters as the output voltage, efficiency, rise time, variable power supply and clock frequency effects were measured.

scholarly journals Topology, analysis, and CMOS implementation of switched-capacitor DC-DC converters

2014 ◽  
Vol 27 (1) ◽  
pp. 41-56 ◽  
Author(s):  
Oi-Ying Wong ◽  
Hei Wong ◽  
Wing-Shan Tam ◽  
Chi-Wah Kok
Keyword(s):  
Large Range ◽  
Supply Voltage ◽  
Charge Pump ◽  
Voltage Regulation ◽  
Voltage Fluctuations ◽  
Topology Analysis ◽  
Charge Pumps ◽  
New Methods ◽  
Dynamic Performances ◽  
Cmos Implementation

This review highlights various design and realization aspects of three commonly used charge pump topologies, namely, the linear, exponential, and the Fibonacci type of charge pumps. We shall outline the new methods developed recently for analyzing the steady and dynamic performances of these circuits. Some practical issues for the CMOS implementation of these charge pump structures will be critically discussed. Finally, some conventional voltage regulation methods for maintaining a stable output under a large range of loading current and supply voltage fluctuations will be proposed.

High Pumping Gain Dickson Charge Pump Using Improved Bootstrapped Technique

2015 ◽  
Vol 764-765 ◽  
pp. 506-510
Author(s):  
Yung Chin Chen
Keyword(s):  
Threshold Voltage ◽  
Output Voltage ◽  
Voltage Drop ◽  
Charge Pump ◽  
Pump Efficiency ◽  
Dc Voltage ◽  
Pumping Efficiency ◽  
High Efficient ◽  
Efficient Charge ◽  
Charge Pump Circuit

This paper proposed an improved bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump in order to get a higher pumping efficiency. It is not only avoid the threshold voltage drop in conventional Dickson charge pump circuits but enable them to generate a higher output voltage. Simulation by HSPICE shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.76 times of it (VOUT=7.14V), the pump efficiency can reaches as high as 95.2%.

Sign in / Sign up

Export Citation Format

Share Document