scholarly journals A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES

2014 ◽  
pp. 16-19
Author(s):  
AAMNA ANIL ◽  
RAVI KUMAR SHARMA
Keyword(s):  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Charge Pumps ◽  
Nonvolatile Memories ◽  
A Charge ◽  
Low Supply Voltage ◽  
Capacitor Charge ◽  
Lower Voltage

A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. Charge pumps have been used in the nonvolatile memories, such as EEPROM and Flash memories, for the programming of the floating-gate devices. They can also be used in the low-supply-voltage switched-capacitor systems that require high voltage to drive the analog switched. This paper includes voltage analysis of different charge pumps. On the basis of voltage analysis a new charge pump is proposed.

scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

Design of a charge pump for high voltage driver applications based on 0.35 μm BCD technology

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740008
Author(s):  
Tiezhu Zhu ◽  
Yuning Zhang ◽  
Rendong Ji
Keyword(s):  
System Theory ◽  
Output Feedback ◽  
High Efficiency ◽  
Supply Voltage ◽  
Output Feedback Control ◽  
Charge Pump ◽  
Control Module ◽  
Simulation Based ◽  
Power Noise ◽  
A Charge

Based on the switched capacitor system theory, a new charge pump is designed as the driver of the H-bridge power circuits. The proposed circuit is added with the output feedback control module to realize the steady output, lower the ripple and power noise, and improve the transforming efficiency. Simulation based on 0.35 [Formula: see text] BCD350GE process demonstrates that the circuit has a ripple voltage as low as 200 mV and reaches a high efficiency up to 70% with a load as much as 20 mA when the supply voltage changes from 8 V to 36 V.

ULTRA-LOW-VOLTAGE GAIN-ENHANCED FOUR-PHASE CHARGE PUMP WITHOUT BODY EFFECT

2014 ◽  
Vol 23 (07) ◽  
pp. 1450104 ◽  
Author(s):  
CHANGLONG LIN ◽  
XINZHUO SUN ◽  
SHILIANG MA ◽  
XIN LU ◽  
KE LIANG ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
The Body ◽  
Cmos Process ◽  
Resistive Load ◽  
Voltage Gain ◽  
Body Effect ◽  
Charge Pumps ◽  
Standard Cmos Process

In this paper, an ultra-low-voltage gain-enhanced four-phase charge pump is proposed. The proposed charge pump is designed in 0.18 μm 1.8 V standard CMOS process with high voltage boosting efficiency when the supply voltage is between 0.5 V and 1.8 V. Moreover, it eliminates the body effect by means of adding two auxiliary substrate switching PMOS transistor. The simulation results show that the proposed charge pump has higher efficiency than the other two low voltage charge pumps when the resistive load is 100 M ohm and the supply voltage is between 0.5 and 1.8 V. A test chip has been realized in a 0.18 μm 1.8 V standard CMOS process. The test results show perfect performance when the supply voltage is between 0.7 and 1.8 V. The proposed charge pump is quite suitable for low power applications.

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

A New Low Voltage Analog Circuit Model for Hodgkin–Huxley Neuron Employing FGMOS Transistors

2018 ◽  
Vol 27 (09) ◽  
pp. 1850141
Author(s):  
Ava Salmanpour ◽  
Ebrahim Farshidi ◽  
Karim Ansari Asl
Keyword(s):  
Analog Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Circuit Model ◽  
Weak Inversion ◽  
Combined Action ◽  
Low Costs ◽  
Low Supply Voltage ◽  
Channel Currents

A low voltage analog VLSI circuit model for Hodgkin–Huxley (HH) neuron cell equations (HH neuron model) is presented. Floating gate MOSFET (FGMOS) transistors in weak inversion region have been used to model HH equations such as gating variables, [Formula: see text] and [Formula: see text] functions and combined action of [Formula: see text], [Formula: see text] and [Formula: see text]. The combination of [Formula: see text], [Formula: see text] and [Formula: see text] controls the Na[Formula: see text] and K[Formula: see text] channel currents. The superiorities of the proposed circuits are low supply voltage, low power consumption, less circuit complexity and as a result, low costs are compared to the previous works. The proposed circuit which uses 24 transistors is simulated in Hspice software using 0.18[Formula: see text] technology and consumes 119[Formula: see text][Formula: see text]W.

scholarly journals Current mismatch reduction in charge pumps using regulated current stealing-injecting transistors for PLLs

2021 ◽  
Vol 24 (1) ◽  
pp. 61
Author(s):  
Mohd Khairi Zulkalnain ◽  
Yan Chiew Wong
Keyword(s):  
Metal Oxide ◽  
Supply Voltage ◽  
Channel Length ◽  
Feedback Mechanism ◽  
Phase Locked Loops ◽  
Voltage Controlled Oscillator ◽  
Op Amp ◽  
Compensation Technique ◽  
A Charge ◽  
Low Supply Voltage

A charge pump for phase locked loops (PLL) with a novel current mismatch compensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The proposed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.

scholarly journals A design of low voltage OPAMP using split-length transistors

2014 ◽  
Vol 17 (1) ◽  
pp. 62-70
Author(s):  
Khanh Trung Le ◽  
Tu Trong Bui ◽  
Hung Duc Le ◽  
Kha Cong Pham
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Feedback Systems ◽  
Advanced Technique ◽  
Low Voltage Operation ◽  
Feedback Compensation ◽  
Indirect Feedback ◽  
Low Supply Voltage

In the paper, we present a design of a low voltage Operation Amplifier (OPAMP) circuit using split-length transistors. Indirect feedback compensation is an advanced technique used to stabilize the operation of an OPAMP. Cascode transistors are usually implemented for indirect feedback systems. However, these transistors are not suitable for low voltage design. In this study, we have taken advantage of split-length transistors and indirect feedback compensation technique to design a high performance OPAMP. As a result, the OPAMP operates not only at low supply voltage but also at high frequency. The OPAMP has been designed and fabricated in a 0.18um CMOS technology. This OPAMP achieves 100 dB gain, 90 MHz unity gain frequency and 60 degrees phase margin at 2 V supply voltage.

DESIGN OF MODIFIED FOUR-PHASE CMOS CHARGE PUMPS FOR LOW-VOLTAGE FLASH MEMORIES

2002 ◽  
Vol 11 (04) ◽  
pp. 393-403 ◽  
Author(s):  
HONGCHIN LIN ◽  
NAI-HSIEN CHEN ◽  
JAINHAO LU
Keyword(s):  
Power Efficiency ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Flash Memories ◽  
Clock Generation ◽  
Charge Pumps ◽  
Main Charge

A new four-phase clock scheme for the four-phase charge pumping circuits using standard 0.5 μm CMOS technology at low supply voltages to generated high boosted voltages is proposed. Boosted clocks without high drivability are applied on the capacitors coupled to the gates of the main charge transfer transistors to compensate body effects. Thus, the high-voltage clock generation circuit can be easily achieved for clock frequency of 10 MHz. Due to the nearly ideal pumping gain per stage, the design methodology to optimize power efficiency is also presented. With the new clock scheme, it can efficiently pump to 9 V at supply voltage of 1 V using 10 stages by simulations, while pump to 4.7 V at supply voltage of 1.5 V using four stages by measurements.

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