scholarly journals Miniaturized GaAs Nanowire Laser with a Metal Grating Reflector

Nanomaterials ◽  
2020 ◽  
Vol 10 (4) ◽  
pp. 680 ◽  
Author(s):  
Wei Wei ◽  
Xin Yan ◽  
Xia Zhang
Keyword(s):  
Three Dimensions ◽  
Nanowire Diameter ◽  
Metal Grating ◽  
Reduced Dimensions ◽  
Gaas Nanowire ◽  
Simulation Results ◽  
On Chip ◽  
High Reflection ◽  
Threshold Gain ◽  
Facet Reflection

This work proposed a miniaturized nanowire laser with high end-facet reflection. The high end-facet reflection was realized by integrating an Ag grating between the nanowire and the substrate. Its propagation and reflection properties were calculated using the finite elements method. The simulation results show that the reflectivity can be as high as 77.6% for a nanowire diameter of 200 nm and a period of 20, which is nearly three times larger than that of the nanowire without a metal grating reflector. For an equal length of nanowire with/without the metal grating reflector, the corresponding threshold gain is approximately a quarter of that of the nanowire without the metal grating reflector. Owing to the high reflection, the length of the nanowire can be reduced to 0.9 μm for the period of 5, resulting in a genuine nanolaser, composed of nanowire, with three dimensions smaller than 1 μm (the diameter is 200 nm). The proposed nanowire laser with a lowered threshold and reduced dimensions would be of great significance in on-chip information systems and networks.

scholarly journals Effect Analysis of Design Variables on the Disc in a Double-Eccentric Butterfly Valve

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Sangmo Kang ◽  
Da-Eun Kim ◽  
Kuk-Kyeom Kim ◽  
Jun-Oh Kim
Keyword(s):  
Pressure Drop ◽  
Maximum Stress ◽  
Optimal Combination ◽  
Three Dimensions ◽  
Butterfly Valve ◽  
Effect Analysis ◽  
Performance Simulation ◽  
Design Variables ◽  
Commercial Package ◽  
Simulation Results

We have performed a shape optimization of the disc in an industrial double-eccentric butterfly valve using the effect analysis of design variables to enhance the valve performance. For the optimization, we select three performance quantities such as pressure drop, maximum stress, and mass (weight) as the responses and three dimensions regarding the disc shape as the design variables. Subsequently, we compose a layout of orthogonal array (L16) by performing numerical simulations on the flow and structure using a commercial package, ANSYS v13.0, and then make an effect analysis of the design variables on the responses using the design of experiments. Finally, we formulate a multiobjective function consisting of the three responses and then propose an optimal combination of the design variables to maximize the valve performance. Simulation results show that the disc thickness makes the most significant effect on the performance and the optimal design provides better performance than the initial design.

How Computational Grid Refinement in Three Dimensions Affects CFD-DEM Results for Psuedo-2D Fluidized Gas-Solid Beds

2017 ◽  
Author(s):  
Annette Volk ◽  
Urmila Ghia
Keyword(s):  
Three Dimensional ◽  
Computational Grid ◽  
Three Dimensions ◽  
Computational Grids ◽  
Grid Refinement ◽  
2D Simulation ◽  
Computational Fluid Dynamics Cfd ◽  
Bed Thickness ◽  
Simulation Results ◽  
Accuracy Of Results

Computational Fluid Dynamics (CFD)-Discrete Element Method (DEM) simulations are designed to model a pseudo-two-dimensional fluidized bed. Bed behavior and accuracy of results are shown to change as the simulations are conducted on increasingly refined computational grids. Trends of the results with grid refinement are reported for both three-dimensional, uniform refinement, and for grid refinement in only the direction of bed thickness. Pseudo-2D simulation results are examined against previously published experimental data to assess relative accuracy compared to fully 3D simulation results. Two drag laws are employed in the simulations, resulting in different trends of results with computational grid refinement. From these results, we present suggestions for accurate model design.

A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS

2013 ◽  
Vol 433-435 ◽  
pp. 1463-1469 ◽  
Author(s):  
Yi Lin Zheng ◽  
Ying Mei Chen ◽  
Jian Wei Gong ◽  
Jian Guo Yao
Keyword(s):  
Laser Diode ◽  
Cmos Technology ◽  
Radio Over Fiber ◽  
Power Gain ◽  
Power Added Efficiency ◽  
Input And Output ◽  
Linear Amplifier ◽  
Simulation Results ◽  
On Chip ◽  
Dynamic Bias

The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.

Noise Bus Modeling in Network on Chip

2018 ◽  
Vol 27 (09) ◽  
pp. 1850149 ◽  
Author(s):  
Moez Balti
Keyword(s):  
Bit Error Rate ◽  
Network On Chip ◽  
Waveform Relaxation ◽  
Signal Source ◽  
Electrical Circuits ◽  
Coupling Noise ◽  
Current Voltage ◽  
Coupled Lines ◽  
Simulation Results ◽  
On Chip

This paper considers the noise modeling of interconnections in on-chip communication. We present an approach to illustrate modeling and simulation of interconnections on chip microsystems that consist of electrical circuits connected to subsystems described by partial differential equations, which are solved independently. A model for energy dissipation in RLC mode is proposed for the switching current/voltage of such on-chip interconnections. The Waveform Relaxation (WR) algorithm is presented in this paper to address limiting in simulating NoCs due to the large number of coupled lines. We describe our approach to the modeling of on-chip interconnections. We present an applicative example of our approach with VHDL-AMS implementations and simulation results. This article analyzes the coupling noise, the bit error rate (BER) as well as the noise as a function of the rise/fall time of the signal source which can significantly limit the scalability of the NoCs.

scholarly journals Damage progression from impact in layered glass modeled with peridynamics

2012 ◽  
Vol 2 (4) ◽  
Author(s):  
Florin Bobaru ◽  
Youn Ha ◽  
Wenke Hu
Keyword(s):  
Spatial Resolution ◽  
Damage Evolution ◽  
Dynamic Interaction ◽  
Stress Waves ◽  
Three Dimensions ◽  
Contact Conditions ◽  
Peridynamic Model ◽  
Simulation Results ◽  
Simple Contact ◽  
Computational Resources

AbstractDynamic fracture in brittle materials has been difficult to model and predict. Interfaces, such as those present in multi-layered glass systems, further complicate this problem. In this paper we use a simplified peridynamic model of a multi-layer glass system to simulate damage evolution under impact with a high-velocity projectile. The simulation results are compared with results from recently published experiments. Many of the damage morphologies reported in the experiments are captured by the peridynamic results. Some finer details seen in experiments and not replicated by the computational model due to limitations in available computational resources that limited the spatial resolution of the model, and to the simple contact conditions between the layers instead of the polyurethane bonding used in the experiments. The peridynamic model uncovers a fascinating time-evolution of damage and the dynamic interaction between the stress waves, propagating cracks, interfaces, and bending deformations, in three-dimensions.

scholarly journals Design and simulation of bio fluidic sensor based on photonic crystal

2014 ◽  
Vol 3 (2) ◽  
pp. 106
Author(s):  
Rajini Gaddam Kesava Reddy ◽  
Sharmila Ashok kumar ◽  
Sankardoss Varadhan
Keyword(s):  
Photonic Crystals ◽  
Photonic Band Gap ◽  
Optical Cavity ◽  
Fdtd Method ◽  
High Sensitivity ◽  
Three Dimensions ◽  
Fluidic Channel ◽  
Optical Cavities ◽  
Fluid Sensor ◽  
On Chip

Photonic crystals are materials patterned with a periodicity in dielectric constant in one, two and three dimensions and associated with Bragg scattering which can create range of forbidden frequencies called Photonic Band Gap (PBG). By optimizing various parameters and creating defects, we will review the design and characterization of waveguides, optical cavities and multi-fluidic channel devices. We have used such waveguides and laser nanocavities as Biosensor, in which field intensity is strongly dependent on the type of biofliud and its refractive index. This design and simulation technique leads to development of a nanophotonic sensor for detection of biofluids. In this paper, we have simulated sensing of biofliud in various photonic defect structures with the help of a numerical algorithm called Finite Difference Time Domain (FDTD) method. The simulation result shows the high sensitivity for the change in the bio-molecular structure. For developing the complete sensor system, we have to use the MEMS technologies to integrate on-chip fluidic transport components with sensing systems. The resulting biofluidic system will have the capability to continuously monitor the concentration of a large number of relevant biological molecules continuously from ambulatory patients. Keywords: FDTD, Photonic Crystals, Bio fluid Sensor, Optical Cavity.

An Analytical Study on Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 534 ◽  
pp. 197-205
Author(s):  
Kiichi Niitsu ◽  
Masato Sakurai ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Daiki Oki ◽  
...  
Keyword(s):  
Power Supply ◽  
Analytical Study ◽  
Cmos Technology ◽  
High Accuracy ◽  
Spice Simulation ◽  
Supply Noise ◽  
Noise Injection ◽  
Simulation Results ◽  
On Chip ◽  
Frequency Detector

This work presents the analytical study on jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. Jitter accumulation in phase frequency detector degrades the accuracy of on-chip jitter measurements, and required to be mitigated. In order to analyze and estimate the jitter accumulation in phase frequency detectors, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that, with a 50 mV power supply noise injection, jitter accumulation can be reduced from 1.03 ps to 0.49 ps (52% reduction) by using an interleaved architecture.

Ethernet Controller and Serial Interface Conversion Technology Based on FPGA

2013 ◽  
Vol 423-426 ◽  
pp. 2671-2674
Author(s):  
Jie Fei Zhang ◽  
Peng Fei Zhan ◽  
Gang Zhang
Keyword(s):  
Data Transmission ◽  
Serial Communication ◽  
Network Data ◽  
Serial Interface ◽  
Communication Controller ◽  
Modularization Design ◽  
Ethernet Controller ◽  
Simulation Results ◽  
On Chip ◽  
Transmission Test

The FPGA-based 10/100M Ethernet MAC controller and universal asynchronous serial communication controller are designed and connected on chip in this paper. Such functions as writing data transmitted by the serial interface to the Ethernet controller and sending them to the network, and serially outputting network data received by the Ethernet controller are implemented and interconnection communications between Ethernet and the serial are achieved, possessing great practical values in system test. Modularization design is performed on the whole system with VHDL in this study, whose hardware application is verified on Xilinx Virtex2P XC2VP30 development board. The simulation results prove that the design has reliability, stability and good applications in the data transmission test.

Deadlock Free Load Balanced Adaptive Routing for Network on Chip (NoC) Systems

2016 ◽  
Vol 13 (10) ◽  
pp. 7592-7598
Author(s):  
J Kalaivani ◽  
B Vinayagasundaram
Keyword(s):  
Packet Loss ◽  
Probability Function ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Communication Architecture ◽  
Data Packets ◽  
Oblivious Routing ◽  
Simulation Results ◽  
On Chip ◽  
Load Balanced

The Network-on-Chip (NoC) systems have emerged in on-chip communication architecture in various fields. To achieve excellent results in Network on Chip (NoC) systems application, the routing must eliminate the deadlock issues from the network. To overcome this issue in the network, in this paper, we propose Deadlock Free Load Balanced Adaptive Routing. In this approach, Oblivious Routing (OR) algorithm is implemented on the channel by using the probability function. The network considers the capacity of the node and tries to maximize the throughput based on the connectivity between the data packets flow and minimize the channel load. A Reconfiguration Protocol is used for the data packets to choose other channel in the network if the deadlock occurs. Simulation results show that this approach reduces the delay and packet loss in the network.

Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 596 ◽  
pp. 176-180
Author(s):  
Kiichi Niitsu ◽  
Kazunori Sakuma ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Nobukazu Takai ◽  
...  
Keyword(s):  
Design Methodology ◽  
Thermal Noise ◽  
Delay Line ◽  
Cmos Technology ◽  
High Accuracy ◽  
Delay Lines ◽  
Spice Simulation ◽  
Simulation Results ◽  
On Chip

This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter generation.

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