Ethernet Controller and Serial Interface Conversion Technology Based on FPGA

2013 ◽  
Vol 423-426 ◽  
pp. 2671-2674
Author(s):  
Jie Fei Zhang ◽  
Peng Fei Zhan ◽  
Gang Zhang
Keyword(s):  
Data Transmission ◽  
Serial Communication ◽  
Network Data ◽  
Serial Interface ◽  
Communication Controller ◽  
Modularization Design ◽  
Ethernet Controller ◽  
Simulation Results ◽  
On Chip ◽  
Transmission Test

The FPGA-based 10/100M Ethernet MAC controller and universal asynchronous serial communication controller are designed and connected on chip in this paper. Such functions as writing data transmitted by the serial interface to the Ethernet controller and sending them to the network, and serially outputting network data received by the Ethernet controller are implemented and interconnection communications between Ethernet and the serial are achieved, possessing great practical values in system test. Modularization design is performed on the whole system with VHDL in this study, whose hardware application is verified on Xilinx Virtex2P XC2VP30 development board. The simulation results prove that the design has reliability, stability and good applications in the data transmission test.

scholarly journals Design and Interfacing of I2C Master with Register and LCD Slaves

2020 ◽  
Vol 9 (4) ◽  
pp. 2355-2360
Keyword(s):  
Data Transmission ◽  
Serial Communication ◽  
Verilog Hdl ◽  
Design Synthesis ◽  
Exchange Of Information ◽  
On Chip ◽  
Multiple Masters

One of the foremost, well-liked, less sophisticated Serial communication standards, I2C; a bus protocol familiarly meant for the exchange of information among the peripherals residing on the constant circuit card, houses two-wires i.e., data and clock for supporting duplex communication between multiple masters and slaves do considered as prominent and efficient in Data transmission. The present work emphasizes on the I2C controller designed for interfacing with slaves, a simple control register of I2C switches/card where the data is written or scan from, subsequently, I2C core implementation on Spartan 3E FPGA, where one of its on-chip peripheral, in this case LCD treated as a slave for performing data transactions. The entire module is designed in Verilog HDL, functional checking is accomplished with the ISIM 10.0b simulator, followed by the design synthesis using Xilinx ISE14.4 tool

A Dicode Signaling Scheme for Capacitively Coupled Interface

2011 ◽  
Vol 497 ◽  
pp. 296-305
Author(s):  
Yasushi Yuminaka ◽  
Kyohei Kawano
Keyword(s):  
Partial Response ◽  
Data Transmission ◽  
High Speed ◽  
Circuit Simulation ◽  
Frequency Bandwidth ◽  
Capacitively Coupled ◽  
Limited Frequency ◽  
Simulation Results ◽  
Response Coding ◽  
The Impact

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.

scholarly journals A Study on the Optimization of Blockchain Hashing Algorithm Based on PRCA

2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
Jinhua Fu ◽  
Sihai Qiao ◽  
Yongzhong Huang ◽  
Xueming Si ◽  
Bin Li ◽  
...  
Keyword(s):  
Supply Chain ◽  
Internet Of Things ◽  
Data Transmission ◽  
Reconfigurable Computing ◽  
Hash Function ◽  
Network Data ◽  
Supply Chain Finance ◽  
Hash Algorithm ◽  
Hashing Function ◽  
Hashing Algorithm

Blockchain is widely used in encrypted currency, Internet of Things (IoT), supply chain finance, data sharing, and other fields. However, there are security problems in blockchains to varying degrees. As an important component of blockchain, hash function has relatively low computational efficiency. Therefore, this paper proposes a new scheme to optimize the blockchain hashing algorithm based on PRCA (Proactive Reconfigurable Computing Architecture). In order to improve the calculation performance of hashing function, the paper realizes the pipeline hashing algorithm and optimizes the efficiency of communication facilities and network data transmission by combining blockchains with mimic computers. Meanwhile, to ensure the security of data information, this paper chooses lightweight hashing algorithm to do multiple hashing and transforms the hash algorithm structure as well. The experimental results show that the scheme given in the paper not only improves the security of blockchains but also improves the efficiency of data processing.

A Small World Routing Protocol in Wireless Sensor Networks

2011 ◽  
Vol 474-476 ◽  
pp. 828-833
Author(s):  
Wen Jun Xu ◽  
Li Juan Sun ◽  
Jian Guo ◽  
Ru Chuan Wang
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Routing Protocol ◽  
Data Transmission ◽  
Small World ◽  
Wireless Sensor ◽  
Small World Network ◽  
Average Delay ◽  
Network Diameter ◽  
Simulation Results

In order to reduce the average path length of the wireless sensor networks (WSNs) and save the energy, in this paper, the concept of the small world is introduced into the routing designs of WSNs. So a new small world routing protocol (SWRP) is proposed. By adding a few short cut links, which are confined to a fraction of the network diameter, we construct a small world network. Then the protocol finds paths through recurrent propagations of weak and strong links. The simulation results indicate that SWRP reduces the energy consumption effectively and the average delay of the data transmission, which leads to prolong the lifetime of both the nodes and the network.

scholarly journals A Novel Hardware Security Architecture: PD-CRP(PUF Database & Challenge-Response Pair) Bloom Filter on Memristor Based PUF

2020 ◽  
Author(s):  
Jungwon Lee ◽  
Seoyeon Choi ◽  
Dayoung Kim ◽  
Yunyoung Choi ◽  
Wookyung Sun
Keyword(s):  
Data Transmission ◽  
Hardware Security ◽  
Bloom Filter ◽  
Transmission Error ◽  
Bloom Filters ◽  
Search Performance ◽  
Security Technology ◽  
Security Environment ◽  
Filter Size ◽  
Simulation Results

Because the development of the internet of things (IoT) requires technology that transfers information between objects without human intervention, the core of IoT security will be secure authentication between devices or between devices and servers. Software-based authentication may be a security vulnerability in IoT, but hardware-based security technology can provide a strong security environment. A physical unclonable functions (PUFs) are a hardware security element suitable for lightweight applications. PUFs can generate challenge-response pairs(CRPs) that cannot be controlled or predicted by utilizing inherent physical variations that occur in the manufacturing process. In particular, pulse width memristive PUF (PWM-PUF) improves security performance by applying different write pulse widths and bank structures. Bloom filter (BF) is probabilistic data structures that answer membership queries using small memories. Bloom filter can improve search performance and reduce memory usage and are used in areas such as networking, security, big data, and IoT. In this paper, we propose a structure that applies Bloom filters based on the PWM-PUF to reduce PUF data transmission errors. The proposed structure uses two different Bloom filter types that store different information and that are located in front of and behind the PWM-PUF, improving security by removing challenges from attacker access. Simulation results show that the proposed structure decreases the data transmission error rate and reuse rate as the Bloom filter size increases, the simulation results also show that the proposed structure improves PWM-PUF security with a very small Bloom filter memory.

scholarly journals Simulation and Measurement Studies of The Vdes System’s Terrestrial Component

2019 ◽  
Vol 26 (1) ◽  
pp. 95-106 ◽  
Author(s):  
Krzysztof Bronk ◽  
Patryk Koncicki ◽  
Adam Lipka ◽  
Dominik Rutkowski ◽  
Błażej Wereszko
Keyword(s):  
Data Transmission ◽  
Data Exchange ◽  
Technical Information ◽  
Theoretical Data ◽  
Current Version ◽  
Coding Gain ◽  
Exchange System ◽  
Measurement Results ◽  
Simulation Results ◽  
Theoretical Results

Abstract In the paper, the measurement and simulation results of the VDES (VHF Data Exchange System) terrestrial component are discussed. It is anticipated that VDES will be one of the major solutions for maritime communications in the VHF band and its performance will be sufficient to fulfill the requirements of the e-navigation applications. The process of the VDES standardization (ITU R, IALA) has not been officially completed yet, but substantial amount of technical information about the future system’s terrestrial component (VDE-TER) is already available. The paper is divided into three general parts: (a) theoretical presentation of the system’s physical layer and the radio channels applicable to VDES, (b) simulation results (BER, BLER, channel delay between two propagation paths and its influence on bit rates) and (c) measurement results (useful ranges, BER). It turned out that in real maritime conditions, the VDES system can offer ranges between 25 and 38 km for the configurations assumed during the measurement campaign. Those results are generally compliant with the theoretical data in the line-of-sight conditions. In the NLOS scenarios, where fading becomes the dominant phenomenon, the discrepancies between the measurements and the theoretical results were more significant. The obtained results confirmed that VDES provides a large coding gain, which significantly improves the performance of data transmission and increases the bit rate compared to the existing maritime radiocommunication solutions. It should be noted that the results presented in the article were used by the IALA while developing the current version of the VDES specification.

A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS

2013 ◽  
Vol 433-435 ◽  
pp. 1463-1469 ◽  
Author(s):  
Yi Lin Zheng ◽  
Ying Mei Chen ◽  
Jian Wei Gong ◽  
Jian Guo Yao
Keyword(s):  
Laser Diode ◽  
Cmos Technology ◽  
Radio Over Fiber ◽  
Power Gain ◽  
Power Added Efficiency ◽  
Input And Output ◽  
Linear Amplifier ◽  
Simulation Results ◽  
On Chip ◽  
Dynamic Bias

The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.

Noise Bus Modeling in Network on Chip

2018 ◽  
Vol 27 (09) ◽  
pp. 1850149 ◽  
Author(s):  
Moez Balti
Keyword(s):  
Bit Error Rate ◽  
Network On Chip ◽  
Waveform Relaxation ◽  
Signal Source ◽  
Electrical Circuits ◽  
Coupling Noise ◽  
Current Voltage ◽  
Coupled Lines ◽  
Simulation Results ◽  
On Chip

This paper considers the noise modeling of interconnections in on-chip communication. We present an approach to illustrate modeling and simulation of interconnections on chip microsystems that consist of electrical circuits connected to subsystems described by partial differential equations, which are solved independently. A model for energy dissipation in RLC mode is proposed for the switching current/voltage of such on-chip interconnections. The Waveform Relaxation (WR) algorithm is presented in this paper to address limiting in simulating NoCs due to the large number of coupled lines. We describe our approach to the modeling of on-chip interconnections. We present an applicative example of our approach with VHDL-AMS implementations and simulation results. This article analyzes the coupling noise, the bit error rate (BER) as well as the noise as a function of the rise/fall time of the signal source which can significantly limit the scalability of the NoCs.

XML Digital Signature Application in Network Test System

2014 ◽  
Vol 513-517 ◽  
pp. 2016-2019
Author(s):  
Xiao Feng Wang
Keyword(s):  
Digital Signature ◽  
Data Transmission ◽  
Data Security ◽  
Digital Signatures ◽  
Test System ◽  
Signature Verification ◽  
Network Data ◽  
Verification Process ◽  
Network Test System ◽  
Xml Digital Signature

This paper describes the concept of XML digital signatures, analyzes the digital signature and the signature verification process, describes the W3C digital signature specification, and studies how to ensure data security in network exam in C #.NET environment. Experiments show that: XML digital signature in network test system ensures the integrity of network data transmission, the identity of verifiability and non-repudiation.

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