Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 596 ◽  
pp. 176-180
Author(s):  
Kiichi Niitsu ◽  
Kazunori Sakuma ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Nobukazu Takai ◽  
...  
Keyword(s):  
Design Methodology ◽  
Thermal Noise ◽  
Delay Line ◽  
Cmos Technology ◽  
High Accuracy ◽  
Delay Lines ◽  
Spice Simulation ◽  
Simulation Results ◽  
On Chip

This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter generation.

An Analytical Study on Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 534 ◽  
pp. 197-205
Author(s):  
Kiichi Niitsu ◽  
Masato Sakurai ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Daiki Oki ◽  
...  
Keyword(s):  
Power Supply ◽  
Analytical Study ◽  
Cmos Technology ◽  
High Accuracy ◽  
Spice Simulation ◽  
Supply Noise ◽  
Noise Injection ◽  
Simulation Results ◽  
On Chip ◽  
Frequency Detector

This work presents the analytical study on jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. Jitter accumulation in phase frequency detector degrades the accuracy of on-chip jitter measurements, and required to be mitigated. In order to analyze and estimate the jitter accumulation in phase frequency detectors, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that, with a 50 mV power supply noise injection, jitter accumulation can be reduced from 1.03 ps to 0.49 ps (52% reduction) by using an interleaved architecture.

A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS

2013 ◽  
Vol 433-435 ◽  
pp. 1463-1469 ◽  
Author(s):  
Yi Lin Zheng ◽  
Ying Mei Chen ◽  
Jian Wei Gong ◽  
Jian Guo Yao
Keyword(s):  
Laser Diode ◽  
Cmos Technology ◽  
Radio Over Fiber ◽  
Power Gain ◽  
Power Added Efficiency ◽  
Input And Output ◽  
Linear Amplifier ◽  
Simulation Results ◽  
On Chip ◽  
Dynamic Bias

The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.

A POWER AND AREA EFFICIENT 65 nm CMOS DELAY-LINE ADC FOR ON-CHIP VOLTAGE SENSING

2013 ◽  
Vol 22 (09) ◽  
pp. 1340014 ◽  
Author(s):  
SIDA AMY SHEN ◽  
SHUANG XIE ◽  
WAI TUNG NG
Keyword(s):  
Power Management ◽  
Delay Line ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Voltage Sensing ◽  
Circuit Performance ◽  
Analog To Digital ◽  
Dynamic Voltage ◽  
On Chip ◽  
Area Efficient

This paper presents a 4-bit windowed delay-line analog-to-digital converter (ADC) implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC consumes 14 μW with an ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

scholarly journals A High Efficiency Li-Ion Battery LDO-Based Charger for Portable Application

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Youssef Ziadi ◽  
Hassan Qjidaa
Keyword(s):  
High Efficiency ◽  
Cmos Technology ◽  
High Accuracy ◽  
Constant Current ◽  
Li Ion Battery ◽  
Constant Voltage ◽  
Battery Charger ◽  
Charging Current ◽  
Li Ion ◽  
Simulation Results

This paper presents a high efficiency Li-ion battery LDO-based charger IC which adopted a three-mode control: trickle constant current, fast constant current, and constant voltage modes. The criteria of the proposed Li-ion battery charger, including high accuracy, high efficiency, and low size area, are of high importance. The simulation results provide the trickle current of 116 mA, maximum charging current of 448 mA, and charging voltage of 4.21 V at the power supply of 4.8–5 V, using 0.18 μm CMOS technology.

scholarly journals A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation

2018 ◽  
Vol 7 (2) ◽  
pp. 104
Author(s):  
Vikas Mittal
Keyword(s):  
Power Supply ◽  
High Frequency ◽  
Design Methodology ◽  
Cmos Technology ◽  
Temperature Variations ◽  
Power Efficient ◽  
Load Variations ◽  
Current Consumption ◽  
Rf Communication ◽  
Simulation Results

The present work addresses the design of power efficient fully self biased OTA using a design methodology based on the  transistor characteristics. This analog module was analyzed, designed and prototyped in TSMS 0.35μm CMOS technology. Simulation results are presented, in order to validate the methodology. The OTA has Gain of 41.35 dB and 3db bandwidth of 138.73 kHz and the UGB of 12.40MHz with the current consumption of 65.50 μA. The circuit does not have need of any DC external biasing circuit, only need to apply VDD (3.3 V). Here self biasing has been introduced with power consumption of 216.15μW. The results have been taken with load variations, temperature variations, and power supply variations. This circuit used in real time high frequency applications as in RF communication.

scholarly journals Efficiency Analysis of Low Power Class-E Power Amplifier

2014 ◽  
Vol 8 (5) ◽  
pp. 19
Author(s):  
Mousa Yousefi ◽  
Ziaadin Daie Koozehkanani ◽  
Jafar Sobhi ◽  
Hamid Jangi ◽  
Nasser Nasirezadeh
Keyword(s):  
Low Power ◽  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Efficiency Analysis ◽  
Simulation Results ◽  
On Chip ◽  
Power Class ◽  
Class E

This paper presents an analysis of effect of inductor and switch losses on output power and efficiency of low power class-E power amplifier. This structure is suitable for integrated circuit implementation. Since on chip inductors have large losses than the other elements, the effect of their losses on efficiency has been investigated. Equations for the efficiency have been derived and plotted versus the value of inductors and switch losses. Derived equations are evaluated using MATLAB. Also, Cadence Spectre has been used for schematic simulation. Results show a fair matching between simulated power loss and efficiency and MATLAB evaluations. Considering the analysis, the proposed power amplifier shows about 13 % improvement in power effiency at 400 MHz and -2 dBm output power. It is simulated in 0.18 ?m CMOS technology.

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

2015 ◽  
Vol 24 (06) ◽  
pp. 1550093 ◽  
Author(s):  
Dengquan Li ◽  
Liang Zhang ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Single Channel ◽  
Mode Selection ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Timing Errors ◽  
Delay Locked Loop ◽  
Simulation Results ◽  
On Chip ◽  
Time Interleaved

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

scholarly journals Transaction credit in the unstructured crowd transaction network

2019 ◽  
Vol 3 (3) ◽  
pp. 267-283
Author(s):  
Zhishuo Liu ◽  
Tian Fang ◽  
Yao Dongxin ◽  
Nianci Kou
Keyword(s):  
Design Methodology ◽  
High Accuracy ◽  
The Internet ◽  
Single Node ◽  
Content Type ◽  
Factors Influencing ◽  
Circle Of Friends ◽  
Simulation Results ◽  
Credit Data ◽  
The One

Purpose Current models of transaction credit in the e-commerce network face many problems, such as the one-sided measurement, low accuracy and insufficient anti-aggression solutions. This paper aims to address these problems by studying the transaction credit problem in the crowd transaction network. Design/methodology/approach This study divides the transaction credit into two parts, direct transaction credit and recommended transaction credit, and it proposes a model based on the crowd transaction network. The direct transaction credit comprehensively includes various factors influencing the transaction credit, including transaction evaluation, transaction time, transaction status, transaction amount and transaction times. The recommendation transaction credit introduces two types of recommendation nodes and constructs the recommendation credibility for each type. This paper also proposes a “buyer + circle of friends” method to store and update the transaction credit data. Findings The simulation results show that this model is superior with high accuracy and anti-aggression. Originality/value The direct transaction credit improves the accuracy of the transaction credit data. The recommendation transaction credit strengthens the anti-aggression of the transaction credit data. In addition, the “buyer + circle of friends” method fully uses the computing of the storage ability of the internet, and it also solves the failure problem of using a single node.

scholarly journals A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 284
Author(s):  
Jiyun Tong ◽  
Sha Wang ◽  
Shuang Zhang ◽  
Mengdi Zhang ◽  
Ye Zhao ◽  
...  
Keyword(s):  
Closed Loop ◽  
Delay Line ◽  
Search Algorithm ◽  
Cmos Technology ◽  
Binary Search ◽  
Delay Lines ◽  
Delay Locked Loop ◽  
Binary Search Algorithm ◽  
Pvt Variations ◽  
Low Jitter

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

Sign in / Sign up

Export Citation Format

Share Document