scholarly journals Deep Submicron EGFET Based on Transistor Association Technique for Chemical Sensing

Sensors ◽  
2019 ◽  
Vol 19 (5) ◽  
pp. 1063 ◽  
Author(s):  
Salvatore Pullano ◽  
Nishat Tasneem ◽  
Ifana Mahbub ◽  
Samira Shamsir ◽  
Marta Greco ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
Power Consumption ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Supply Voltage ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Sensitivity ◽  
Current Sensitivity ◽  
Effect Transistor

Extended-gate field-effect transistor (EGFET) is an electronic interface originally developed as a substitute for an ion-sensitive field-effect transistor (ISFET). Although the literature shows that commercial off-the-shelf components are widely used for biosensor fabrication, studies on electronic interfaces are still scarce (e.g., noise processes, scaling). Therefore, the incorporation of a custom EGFET can lead to biosensors with optimized performance. In this paper, the design and characterization of a transistor association (TA)-based EGFET was investigated. Prototypes were manufactured using a 130 nm standard complementary metal-oxide semiconductor (CMOS) process and compared with devices presented in recent literature. A DC equivalence with the counterpart involving a single equivalent transistor was observed. Experimental results showed a power consumption of 24.99 mW at 1.2 V supply voltage with a minimum die area of 0.685 × 1.2 mm2. The higher aspect ratio devices required a proportionally increased die area and power consumption. Conversely, the input-referred noise showed an opposite trend with a minimum of 176.4 nVrms over the 0.1 to 10 Hz frequency band for a higher aspect ratio. EGFET as a pH sensor presented further validation of the design with an average voltage sensitivity of 50.3 mV/pH, a maximum current sensitivity of 15.71 mA1/2/pH, a linearity higher than 99.9%, and the possibility of operating at a lower noise level with a compact design and a low complexity.

scholarly journals Logic-in-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor

2022 ◽  
Author(s):  
Eunwoo Baek ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Supply Voltage ◽  
Silicon Nanowire ◽  
Input Voltage ◽  
Oxide Semiconductor ◽  
High Voltage Gain ◽  
Static Power ◽  
Effect Transistor

Abstract In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). Further, we investigated the hybrid logic and memory operations of the inverter using mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption.

scholarly journals Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1303
Author(s):  
Hoontaek Lee ◽  
Junsoo Kim ◽  
Kumjae Shin ◽  
Wonkyu Moon
Keyword(s):  
Signal Processing ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Complementary Metal Oxide Semiconductor ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Effect Transistor

We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The - characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.

A Study on the Optimization of Deep-Trench Super Junction Metal Oxide Semiconductor Field-Effect Transistor

2021 ◽  
Vol 16 (5) ◽  
pp. 781-785
Author(s):  
Yoon-Young Huh ◽  
Jong-Mun Choi ◽  
Jung-Min Kim ◽  
Ey-Goo Kang ◽  
Hun-Suk Chung
Keyword(s):  
Power Consumption ◽  
Breakdown Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Devices ◽  
Deep Trench ◽  
Trade Off ◽  
Effect Transistor

Power metal oxide semiconductor field-effect transistor is a switching device designed to handle large power consumption; it enables fast switching, resulting in low power consumption. Power devices are used as important components that determine the operation and performance of electrically powered products such as home appliances, smartphones, and automobiles. Power devices must be able to block high voltage so that current does not flow in the off state, have no power consumption in the on state, and have a small resistance so that high current can flow. For high efficiency, power loss must be minimized and resistance must be reduced during the turn-on state. To increase the breakdown voltage, the thickness and resistivity of the N-drift region must be increased. However, owing to the trade-off relationship, as the breakdown voltage increases, the on-resistance also increases. The super junction structure was proposed to improve this trade-off relationship. In this study, a process simulation using TCAD tool was carried out. Similar to the multi-epitaxial process, the P-pillar was divided into several layers, and the value of each concentration was specified. Thus, the charge balance of the pillar regions was achieved. For the maximum breakdown voltage characteristics and minimum on-resistance characteristics of the deep-trench super junction MOSFET, an experiment was conducted to optimize the cell pitch and pillar of the super junction MOSFET using a five-deep trench.

Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization

1987 ◽  
Vol 65 (8) ◽  
pp. 982-986
Author(s):  
J. Marcoux ◽  
J. Orchard-Webb ◽  
J. F. Currie
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Drain Voltage ◽  
Cmos Inverter ◽  
Effect Transistor

We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

scholarly journals Extended gate field-effect-transistor for sensing cortisol stress hormone

2021 ◽  
Vol 2 (1) ◽  
Author(s):  
Shokoofeh Sheibani ◽  
Luca Capua ◽  
Sadegh Kamaei ◽  
Sayedeh Shirin Afyouni Akbari ◽  
Junrui Zhang ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Dynamic Range ◽  
Voltage Sensitivity ◽  
Debye Screening Length ◽  
Current Sensitivity ◽  
Human Sweat ◽  
Wide Range ◽  
Label Free Detection ◽  
Effect Transistor

AbstractCortisol is a hormone released in response to stress and is a major glucocorticoid produced by adrenal glands. Here, we report a wearable sensory electronic chip using label-free detection, based on a platinum/graphene aptamer extended gate field effect transistor (EG-FET) for the recognition of cortisol in biological buffers within the Debye screening length. The device shows promising experimental features for real-time monitoring of the circadian rhythm of cortisol in human sweat. We report a hysteresis-free EG-FET with a voltage sensitivity of the order of 14 mV/decade and current sensitivity up to 80% over the four decades of cortisol concentration. The detection limit is 0.2 nM over a wide range, between 1 nM and 10 µM, of cortisol concentrations in physiological fluid, with negligible drift over time and high selectivity. The dynamic range fully covers those in human sweat. We propose a comprehensive analysis and a unified, predictive analytical mapping of current sensitivity in all regimes of operation.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals 4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim
Keyword(s):  
Dynamic Characteristics ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Switching Speed ◽  
Polysilicon Gate ◽  
Effect Transistor ◽  
Switching Characteristics

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

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