scholarly journals A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 241 ◽  
Author(s):  
Min Qi ◽  
An-qiang Guo ◽  
Dong-hai Qiao
Keyword(s):  
Integrated Circuit ◽  
Sampling Technique ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Frequency Noise ◽  
Voltage Reference ◽  
Noise Floor ◽  
Mems Sensor ◽  
Output Noise

This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.

scholarly journals Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1205 ◽  
Author(s):  
Iván Zamora ◽  
Eyglis Ledesma ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
Integrated Circuit ◽  
Imaging System ◽  
Ultrasonic Transducer ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Axial Distance ◽  
Cmos Integrated Circuit ◽  
Front End ◽  
Analog Front End

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

scholarly journals Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7280
Author(s):  
Xiangyu Li ◽  
Yangong Zheng ◽  
Xiangyan Kong ◽  
Yupeng Liu ◽  
Danling Tang
Keyword(s):  
High Precision ◽  
Closed Loop ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
High Signal ◽  
Cmos Process ◽  
Frequency Noise ◽  
Interface Circuit ◽  
Noise Characteristics ◽  
Mems Accelerometers

High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.

scholarly journals Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

2020 ◽  
Vol 10 (1) ◽  
pp. 348 ◽  
Author(s):  
Donggeun You ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Low Noise ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Frequency Noise ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chopper Stabilization ◽  
Total Power Consumption

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

scholarly journals A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

2020 ◽  
Vol 10 (1) ◽  
pp. 399 ◽  
Author(s):  
Kwonsang Han ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Operational Amplifier ◽  
Wheatstone Bridge ◽  
Input Resistance ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Readout Integrated Circuit ◽  
Chopper Stabilization

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

scholarly journals Fully Differential Chopper-Stabilized Multipath Current-Feedback Instrumentation Amplifier with R-2R DAC Offset Adjustment for Resistive Bridge Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 63 ◽  
Author(s):  
Yongsu Kwon ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Current Feedback ◽  
Readout Integrated Circuit ◽  
Fully Differential ◽  
Chopper Stabilization ◽  
Rejection Ratio

A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.

A High-Performance Interface ASIC for Quartz Rate Sensor

2011 ◽  
Vol 483 ◽  
pp. 471-474
Author(s):  
Wei Ping Chen ◽  
Qing Yi Wang ◽  
Liang Yin ◽  
Zhi Ping Zhou
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Performance ◽  
Low Noise ◽  
Stable Operation ◽  
Cmos Process ◽  
Test Results ◽  
Bias Stability ◽  
Output Noise ◽  
Rate Sensor

In this work, an ASIC interface for quartz rate sensor (QRS) is introduced. Based on 0.6μm 18V N-well CMOS process, it is the first to be realized in the domestic. This chip has a minimized size of 5×4.4mm2. Compared with traditional interface constructed by separate devices, such interface implemented with integrated circuits is advantageous in size and power consumption. This satisfies the requirements of miniature and low power consumption in space industry and military domain. The test results show that this interface features low noise, high linearity, and stable operation. Integrated with the sensor, the entire system presents high performance in short term bias stability, nonlinearity, output noise, bias variation over temperature, and power consumption.

scholarly journals A Fully Integrated 64-Channel Recording System for Extracellular Raw Neural Signals

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2726
Author(s):  
Xiangwei Zhang ◽  
Quan Li ◽  
Chengying Chen ◽  
Yan Li ◽  
Fuqiang Zuo ◽  
...  
Keyword(s):  
Harmonic Distortion ◽  
Field Potential ◽  
Low Noise ◽  
Recording System ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Neural Signals ◽  
Fully Integrated ◽  
Rail To Rail

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm2 and is packaged in a QFN−88 of 10 × 10 mm2. Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μVrms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA

2013 ◽  
Vol 22 (09) ◽  
pp. 1340015 ◽  
Author(s):  
YAJING ZHANG ◽  
WENGAO LU ◽  
GUANNAN WANG ◽  
ZHONGJIAN CHEN ◽  
YACONG ZHANG
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Low Noise ◽  
Cmos Process ◽  
Readout Integrated Circuit ◽  
Analog To Digital Conversion ◽  
Amplifier Design

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

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