IMPLEMENTATION OF LDPC/RS CONCATENATED CODES ON FPGA

2020 ◽  
Author(s):  
М.Ю. Зинченко ◽  
А.М. Левадний ◽  
Ю.А. Гребенко
Keyword(s):  
Integrated Circuits ◽  
Ldpc Code ◽  
Concatenated Codes ◽  
Programmable Logic ◽  
Parity Check ◽  
Error Level ◽  
Experimental Stand ◽  
Low Density Parity Check ◽  
Reed Solomon Code ◽  
Residual Errors

Представлены результаты разработки каскадного кодека на ПЛИС с внутренним низкоплотностным (НП) кодом стандарта DVB-S2 и внешним кодом Рида-Соломона, позволяющим полностью исключить явление остаточного уровня ошибок.В программируемых логических интегральных схемах (ПЛИС) были реализованы кодер НП-кода с алгоритмом кодирования нерегулярное повторение с накоплением и декодер с модифицированным алгоритмом минимум-сумм . Проведена оценка влияния остаточного уровня ошибок на качество декодирования. Приведены описания разработанной архитектуры, экспериментального стенда и используемые ресурсы ПЛИС. The paper presents the results of the development of a cascade codec on FPGAs with an internal low-density parity-check (LDPC) code of the DVB-S2 standard and an external Reed-Solomon code, that completely eliminates the phenomenon of residual errors. LDPC-code encoder with an irregular repetition with accumulation encoding algorithm and a decoder with a modified minimum sums algorithm were implemented in programmable logic integrated circuits (FPGA). The influence of the residual error level on the decoding quality is estimated. The paper presents the developed architecture, a description of the experimental stand and the FPGA resources.

scholarly journals Hardwarearchitektur für einen universellen LDPC Decoder

2009 ◽  
Vol 7 ◽  
pp. 213-218
Author(s):  
C. Beuschel ◽  
H.-J. Pfleiderer
Keyword(s):  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Wird Eine ◽  
Ldpc Decoder ◽  
Low Density Parity Check

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel

2013 ◽  
Vol 347-350 ◽  
pp. 1864-1867
Author(s):  
Ning Hao ◽  
Yang An Zhang ◽  
Jin Nan Zhang ◽  
Ming Lun Zhang ◽  
Xue Guang Yuan
Keyword(s):  
High Speed ◽  
System Simulation ◽  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Coherent Light ◽  
Line System ◽  
Low Density Parity Check ◽  
Atmospheric Channel ◽  
Ber Performance

Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.

scholarly journals Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm

2018 ◽  
Vol 7 (03) ◽  
pp. 23781-23784
Author(s):  
Rajarshini Mishra
Keyword(s):  
Variance Estimation ◽  
Cyclic Codes ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Xilinx Fpga

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

Performance Comparison Between Low–Density Parity–Check And Reed–Solomon Codes Using Wireless Image Transmission System

2012 ◽  
Author(s):  
Ierwan Ab. Karim ◽  
Abdul Karem Hussein Mohammed Almawgani ◽  
Mohd Fadzli Mohd Salleh
Keyword(s):  
Ldpc Code ◽  
Image Transmission ◽  
Transmission System ◽  
Low Density ◽  
Grayscale Image ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Awgn Channel ◽  
Wireless Image Transmission

Dalam kertas ini prestasi kod ketumpatan–rendah kesetaratan–semak (LDPC) dan kod Reed–Solomon (RS) telah dianalisis dengan menggunakan sistem penghantaran imej tanpa wayar. Sistem ini menggunakan salur penambahan Gaussian hinggar putih (AWGN). Dalam kerja ini, imej kelabu telah telah digunakan sebagai punca kemasukan daya. Kualiti imej kelabu yang dibina semula selepas saluran penyahkodan adalah diukur dengan menggunakan puncak nisbah isyarat–hinggar (PSNR) dengan membandingkan imej yang dibina semula dengan kemasukan imej asal. Keputusan penyelakuan menunjukkan prestasi sistem penghantaran imej dengan menggunakan kod LDPC sentiasa mengatasi prestasi sistem yang menggunakan kod RS dalam salur AWGN. Kualiti keluaran imej kelabu adalah dianggap bagus sekiranya nilai PSNR melebihi 30 dB. Kata kunci: Sistem penghantaran imej tanpa wayar; kod LDPC; kod Reed Solomon; salur AGWN In this paper the performance of Low–Density Parity–Check (LDPC) and Reed–Solomon (RS) codes are analyzed using a wireless image transmission system. The system utilizes the Additive White Gaussian Noise (AWGN) channel. In this work, a grayscale image is used as the input data source. The quality of the reconstructed grayscale image after the channel decoder is measured using the Peak Signal to Noise Ratio (PSNR) by comparing the reconstructed image with the input grayscale image. Simulation results show that the performance of image transmission system using LDPC code is always outperformed the system with RS code in AWGN channel. The quality of output grayscale image is considered good if the value of the PSNR is above 30 dB. Key words: Wiresless image transmission system; LDPC code; Reed Solomon code; AWGN channel

Reduced decoding time of LDPC code using convolutional code with Vitrebi decoding in Underwater Communication

2018 ◽  
Vol 7 (2.25) ◽  
pp. 167
Author(s):  
Krishnamoorthy N.R ◽  
Ramadevi R ◽  
Marshiana M ◽  
Sujatha Kumaran
Keyword(s):  
No Value ◽  
Convolutional Code ◽  
Ldpc Code ◽  
Code Rate ◽  
Underwater Communication ◽  
Parity Check ◽  
Minimal Error ◽  
Ldpc Decoding ◽  
Low Density Parity Check ◽  
High Code Rate

Low Density Parity Check code is the more efficient technique to attain the minimal error rate in the underwater channel. To reduce the processing delay in the LDPC decoding, convolutional code with high code rate is used. The result showed that the BER of 10-4 can be obtained with Eb/No value of 20 for code rate of ½ and 12 for code rate of 1/8. It is also showed in result that the decoding time is reduced one-third for data size of 500 and one-tenth for the data size of 1500 bits.  

Enhanced Performances of W/S SAC-OCDMA System Using LDPC Code

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
A. Bouarfa ◽  
M. Kandouci ◽  
S. Bojanic
Keyword(s):  
Bit Error Rate ◽  
Code Division Multiple Access ◽  
Multiple Access ◽  
Ldpc Code ◽  
Two Dimensional ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Spectral Coding ◽  
Code Division Multiple ◽  
Better Than

AbstractIn an incoherent optical code division multiple access (OCDMA) system using amplitude spectral coding (SAC), which exceeds 1.5 Gbps, it is difficult or impossible to make a transmission with a bit error rate better than 10–9. For this, it is necessary to associate an error correction code (ECC) to the SAC-OCDMA system. In this paper, we proposed an architecture of a two-dimensional SAC-OCDMA system (spectral (w) and spatial (s)) using multi-diagonal code (MD) as spreading code and low-density parity check code (LDPC) as ECC. According to the properties of the MD code and the proposed architecture, the phase induced intensity noise is eliminated, which has improved the performance of the system. The theoretically results shows that LDPC/2D-SAC-OCDMA allowing more than 40 users to be multiplexed compared to a non-coded 2D SAC-OCDMA system. This combination allowed us to increase the cardinality of the LDPC/SAC-OCDMA (W/S) system without using an optical hard limiter.

scholarly journals Design and implementation of log domain decoder

2020 ◽  
Vol 10 (2) ◽  
pp. 1454
Author(s):  
Mahmood Farhan Mosleh ◽  
Fadhil Sahib Hasan ◽  
Ruaa Majeed Azeez
Keyword(s):  
Hardware Implementation ◽  
Ldpc Code ◽  
Parity Check ◽  
Robust Performance ◽  
System Generator ◽  
High Data ◽  
Low Density Parity Check ◽  
Communications Systems ◽  
Long Run ◽  
Log Domain

Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex 7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs high data rate with very low BER.

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