A novel 1T2R self-reference physically unclonable function suitable for advanced logic nodes for high security level applications

2021 ◽  
Author(s):  
Yu-Hsuan Lin ◽  
Dai-Ying Lee ◽  
Ming-Hsiu Lee ◽  
Po-Hao Tseng ◽  
Wei-Chen Chen ◽  
...  
Keyword(s):  
Random Access ◽  
Resistive Random Access Memory ◽  
Linear Feedback ◽  
Security Level ◽  
Random Number Generators ◽  
High Data ◽  
System Integrity ◽  
High Security Level ◽  
The Impact ◽  
Self Reference

Abstract A self-reference resistive random access memory (ReRAM)-based 1T2R (1-transistor-2-ReRAM) physically unclonable function (PUF) is proposed to provide hardware security feature for electrical products in the IoT/5G era. There are four advantages from the proposed structure: (1) small cell size; (2) intrinsic randomness; (3) no programming circuit; (4) no data retention concern. The conduction mechanism, temperature dependency, and read fluctuation of pristine ReRAM device are studied. An information-address separation scheme is proposed which not only reduces the impact of the read noise and the temperature effect, but also improves the system integrity against hardware attack. The proposed 1T2R PUF unit also has great potential for using as the random seed for linear feedback shift register (LFSR) in pseudo random number generators (PRNG) with high unpredictability, good randomness, and high data rate.

scholarly journals An Efficient Method for Secure ECG Feature based Cryptographic Key Generation

2019 ◽  
Vol 8 (12) ◽  
pp. 159-164
Keyword(s):  
Normal Sinus Rhythm ◽  
Linear Feedback ◽  
Security Level ◽  
Pseudorandom Number Generator ◽  
Random Number Generators ◽  
Appearance Time ◽  
Normal Sinus ◽  
Myocardial Infraction ◽  
Cryptographic Keys ◽  
Cryptographic Key

A novel method to generate ECG feature oriented cryptographic keys is proposed. Due to the advantage of the uniqueness and randomness properties of ECG’s main feature, this feature is achieved. As the production of key depends on four reference- free ECG main features, Low-latency property is obtained. These features are obtained in short time. This process is referred as (SEF)-based cryptographic key production. The SEF has the following features like: 1) identifying the appearance time of ECG’s fiducial values by means of Daubechies wavelet transform to calculate ECG’s main features conversely; 2) A dynamic method is used to denote the best quantity of bits that can be obtained from the main ECG feature, which consists of PR, RR, PP, QT, and ST time periods; 3) Generating cryptographic keys by the ECG features extracted in the method mentioned above and 4) Making the SEF method as strong with cryptographically secure pseudo-random number generators. Fibonacci linear feedback shift register and recent encryption traditional algorithms are executed as the pseudorandom number generator to improve the safety stage of the produced cryptographic keys. This method is executed to 239 subjects’ ECG signals consisting of normal sinus rhythm, arrhythmia, atrial brillation, and myocardial infraction. Normal ECG rhythms have slightly better randomness when compare with the abnormal.The output results proves that the SEF method is faster than the present existing key production methods. It produces higher security level when compared to existing methods

Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory

2016 ◽  
Vol 1 (6) ◽  
Author(s):  
Amit Prakash ◽  
Hyunsang Hwang
Keyword(s):  
Low Cost ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Comprehensive Analysis ◽  
Multiple Resistance ◽  
Access Memory ◽  
Physical Mechanisms ◽  
Reliability Characteristics ◽  
The Impact

Abstract Multilevel per cell (MLC) storage in resistive random access memory (ReRAM) is attractive in achieving high-density and low-cost memory and will be required in future. In this chapter, MLC storage and resistance variability and reliability of multilevel in ReRAM are discussed. Different MLC operation schemes with their physical mechanisms and a comprehensive analysis of resistance variability have been provided. Various factors that can induce variability and their effect on the resistance margin between the multiple resistance levels are assessed. The reliability characteristics and the impact on MLC storage have also been assessed.

scholarly journals Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 614
Author(s):  
Zhisheng Chen ◽  
Renjun Song ◽  
Qiang Huo ◽  
Qirui Ren ◽  
Chenrui Zhang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Current Model ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Storage ◽  
Access Memory ◽  
Leakage Currents ◽  
The Impact

Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays.

scholarly journals Nonideal resistive and synaptic characteristics in Ag/ZnO/TiN device for neuromorphic system

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Jongmin Park ◽  
Hojeong Ryu ◽  
Sungjun Kim
Keyword(s):  
Resistive Switching ◽  
Random Access ◽  
High Resistance State ◽  
Resistive Random Access Memory ◽  
Bipolar Resistive Switching ◽  
Applied Pulse ◽  
Negative Effect ◽  
Endurance Tests ◽  
Resistance State ◽  
The Impact

AbstractIdeal resistive switching in resistive random-access memory (RRAM) should be ensured for synaptic devices in neuromorphic systems. We used an Ag/ZnO/TiN RRAM structure to investigate the effects of nonideal resistive switching, such as an unstable high-resistance state (HRS), negative set (N-set), and temporal disconnection, during the set process and the conductance saturation feature for synaptic applications. The device shows an I–V curve based on the positive set in the bipolar resistive switching mode. In 1000 endurance tests, we investigated the changes in the HRS, which displays large fluctuations compared with the stable low-resistance state, and the negative effect on the performance of the device resulting from such an instability. The impact of the N-set, which originates from the negative voltage on the top electrode, was studied through the process of intentional N-set through the repetition of 10 ON/OFF cycles. The Ag/ZnO/TiN device showed saturation characteristics in conductance modulation according to the magnitude of the applied pulse. Therefore, potentiation or depression was performed via consecutive pulses with diverse amplitudes. We also studied the spontaneous conductance decay in the saturation feature required to emulate short-term plasticity.

scholarly journals Exploring the Impact of Variability in Resistance Distributions of RRAM on the Prediction Accuracy of Deep Learning Neural Networks

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 414 ◽  
Author(s):  
Nagaraj Prabhu ◽  
Desmond Loy Jia Jun ◽  
Putu Dananjaya ◽  
Wen Lew ◽  
Eng Toh ◽  
...  
Keyword(s):  
Neural Network ◽  
Deep Learning ◽  
Prediction Accuracy ◽  
Random Access ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Device Resistance ◽  
Measured Resistance ◽  
Deep Learning Neural Network ◽  
The Impact

In this work, we explore the use of the resistive random access memory (RRAM) device as a synapse for mimicking the trained weights linking neurons in a deep learning neural network (DNN) (AlexNet). The RRAM devices were fabricated in-house and subjected to 1000 bipolar read-write cycles to measure the resistances recorded for Logic-0 and Logic-1 (we demonstrate the feasibility of achieving eight discrete resistance states in the same device depending on the RESET stop voltage). DNN simulations have been performed to compare the relative error between the output of AlexNet Layer 1 (Convolution) implemented with the standard backpropagation (BP) algorithm trained weights versus the weights that are encoded using the measured resistance distributions from RRAM. The IMAGENET dataset is used for classification purpose here. We focus only on the Layer 1 weights in the AlexNet framework with 11 × 11 × 96 filters values coded into a binary floating point and substituted with the RRAM resistance values corresponding to Logic-0 and Logic-1. The impact of variability in the resistance states of RRAM for the low and high resistance states on the accuracy of image classification is studied by formulating a look-up table (LUT) for the RRAM (from measured I-V data) and comparing the convolution computation output of AlexNet Layer 1 with the standard outputs from the BP-based pre-trained weights. This is one of the first studies dedicated to exploring the impact of RRAM device resistance variability on the prediction accuracy of a convolutional neural network (CNN) on an AlexNet platform through a framework that requires limited actual device switching test data.

The Impact of RTN Signal on Array Level Resistance Fluctuation of Resistive Random Access Memory

2018 ◽  
Vol 39 (5) ◽  
pp. 676-679 ◽  
Author(s):  
Danian Dong ◽  
Jing Liu ◽  
Yuduo Wang ◽  
Xiaoxin Xu ◽  
Peng Yuan ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
The Impact ◽  
Level Resistance

Effect of Conductive Filament Temperature on ZrO2 based Resistive Random Access Memory Devices

2020 ◽  
Vol 12 (2) ◽  
pp. 02008-1-02008-4
Author(s):  
Pramod J. Patil ◽  
◽  
Namita A. Ahir ◽  
Suhas Yadav ◽  
Chetan C. Revadekar ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Devices ◽  
Access Memory ◽  
Conductive Filament ◽  
Filament Temperature

scholarly journals Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
High Performance ◽  
Conduction Mechanism ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Switching Behavior ◽  
Access Memory ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Limited Conduction

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

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