scholarly journals Performance Analysis of Non-Identical Master Slave Flip Flops at 65nm Node

2019 ◽  
Vol 9 (1S) ◽  
pp. 18-21
Keyword(s):  
Performance Analysis ◽  
Supply Voltage ◽  
Hold Time ◽  
Setup Time ◽  
Percentage Reduction ◽  
Flip Flop ◽  
Logic Structure

This paper presents the performance analysis of the different master slave flip flop reported and comparison of their parameters such as power, area, delay setup time and hold time. To reduce the number of transistor count various logic structure mater slave design have been proposed that results reduction in total area of the flip flop. Advantage and disadvantage of the each flip flop has been discussed. Process corner analysis of all flip flop is also presented at supply voltage of 0.7 volts at 27°C temperature. Percentage reduction in power and speed of operation i.e. frequency are discussed

Study on Performance Analysis of CMOS RF front-end circuits for 2.4GHz Wireless Applications

2012 ◽  
pp. 68-73
Author(s):  
M. Sumathi ◽  
S. Malarvizhi
Keyword(s):  
Performance Analysis ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Design System ◽  
Wireless Applications ◽  
Front End ◽  
Trade Offs ◽  
Front End Circuits

In this paper, low voltage design concepts and new CMOS front-end circuits for 2.4GHz wireless applications are presented. The performances of these circuits are analysed and compared with other existing structures using TSMC 0.18-μm CMOS technology scale. The design trade-offs between impedance matching, power gain and noise figure of low-noise amplifiers are highlighted. The advantage of the introduced mixer topology is expressed in terms of conversion gain, noise figure and linearity. At a supply voltage of 1.8V, the design and performance analysis have been performed using Agilent’s Advanced Design System (ADS2009) software.

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

2013 ◽  
Vol 21 (6) ◽  
pp. 1175-1179 ◽  
Author(s):  
Hiroshi Fuketa ◽  
Koji Hirairi ◽  
Tadashi Yasufuku ◽  
Makoto Takamiya ◽  
Masahiro Nomura ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Flip Flop

P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1919-1924 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Gate Oxide ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Power Supply Voltage ◽  
Flip Flop ◽  
Nanometer Cmos ◽  
P Type ◽  
Cmos Processes

With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.

Performance analysis of the Josephson DC flip-flop

1992 ◽  
Vol 2 (3) ◽  
pp. 148-155 ◽  
Author(s):  
Y. Hatano ◽  
H. Nagaishi ◽  
K. Nakahara ◽  
U. Kawabe
Keyword(s):  
Performance Analysis ◽  
Flip Flop

An Experimental Study of Metastability-Induced Glitching Behavior

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940006
Author(s):  
Thomas Polzer ◽  
Florian Huemer ◽  
Andreas Steininger
Keyword(s):  
Decay Constant ◽  
Supply Voltage ◽  
Careful Consideration ◽  
Experimental Measurements ◽  
Measurement Circuit ◽  
Flip Flop ◽  
Systems On Chip ◽  
Voltage Dependent ◽  
Modeling Theory ◽  
On Chip

The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant [Formula: see text] is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.

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