Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

2013 ◽  
Vol 21 (6) ◽  
pp. 1175-1179 ◽  
Author(s):  
Hiroshi Fuketa ◽  
Koji Hirairi ◽  
Tadashi Yasufuku ◽  
Makoto Takamiya ◽  
Masahiro Nomura ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Flip Flop

P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1919-1924 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Gate Oxide ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Power Supply Voltage ◽  
Flip Flop ◽  
Nanometer Cmos ◽  
P Type ◽  
Cmos Processes

With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.

An Experimental Study of Metastability-Induced Glitching Behavior

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940006
Author(s):  
Thomas Polzer ◽  
Florian Huemer ◽  
Andreas Steininger
Keyword(s):  
Decay Constant ◽  
Supply Voltage ◽  
Careful Consideration ◽  
Experimental Measurements ◽  
Measurement Circuit ◽  
Flip Flop ◽  
Systems On Chip ◽  
Voltage Dependent ◽  
Modeling Theory ◽  
On Chip

The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant [Formula: see text] is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.

scholarly journals Performance Analysis of Non-Identical Master Slave Flip Flops at 65nm Node

2019 ◽  
Vol 9 (1S) ◽  
pp. 18-21
Keyword(s):  
Performance Analysis ◽  
Supply Voltage ◽  
Hold Time ◽  
Setup Time ◽  
Percentage Reduction ◽  
Flip Flop ◽  
Logic Structure

This paper presents the performance analysis of the different master slave flip flop reported and comparison of their parameters such as power, area, delay setup time and hold time. To reduce the number of transistor count various logic structure mater slave design have been proposed that results reduction in total area of the flip flop. Advantage and disadvantage of the each flip flop has been discussed. Process corner analysis of all flip flop is also presented at supply voltage of 0.7 volts at 27°C temperature. Percentage reduction in power and speed of operation i.e. frequency are discussed

Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage

2021 ◽  
Vol 16 (4) ◽  
pp. 602-611
Author(s):  
A. N. Duraivel ◽  
B. Paulchamy ◽  
K. Mahendrakan
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Supply Voltage ◽  
Clock Cycle ◽  
The State ◽  
High Threshold ◽  
Clock Signal ◽  
Signal Transfer ◽  
Flip Flop ◽  
Sleep Transistors

Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.

Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS

2015 ◽  
Vol 4 (3) ◽  
pp. 178
Author(s):  
Ajeesh Kumar ◽  
N. Saraswathi
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Circuits ◽  
Flip Flop ◽  
Sleep Transistors ◽  
Power Delay Product ◽  
Charge Mode ◽  
Logic Level

This paper introduces a Low Power Dual DynamicNode FlipFlop(DDFF) using Sleep Transistor with NMOS. Theproposed design retains the logic level till the end of evaluation and pre-charge mode. The low power DDFF architecturethat combines the advantages of dynamic and static CMOSstructures. The Sleep Transistors approach are used for leakagepower reduction. It reduces leakage current in ideal mode.The performance of the proposed flip flop was compared withthe conventional dual dynamic node flip flop (DDFF) in 90nmCMOS technology with 1.2v supply voltage at room temperatures.Also, conventional DDFF and DDFF using Sleep Transistor withNMOS are compared with other complicated designs and realizesby a 4-bit Johnson up and down counter. The performanceimprovements indicates that the proposed designs are suited formodern high-performance CMOS circuits where leakage powerand power delay product overhead are of major concern

A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

2020 ◽  
Vol 15 (1) ◽  
pp. 136-141
Author(s):  
Xianghong Zhao ◽  
Jieyu Zhao ◽  
WeiMing Cai
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
General Structure ◽  
Effective Solution ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Logic Functions ◽  
Structure And Design

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes

Integration ◽  
2014 ◽  
Vol 47 (3) ◽  
pp. 318-328 ◽  
Author(s):  
Qing Xie ◽  
Yanzhi Wang ◽  
Massoud Pedram
Keyword(s):  
Supply Voltage ◽  
Flip Flop ◽  
Soft Edge

INTEGRATED WIDE-BAND CMOS DUOBINARY TRANSMITTER FOR OPTICAL COMMUNICATION SYSTEMS

2005 ◽  
Vol 15 (03) ◽  
pp. 513-523
Author(s):  
RUI TAO ◽  
MANFRED BERROTH
Keyword(s):  
Optical Fibers ◽  
Communication Systems ◽  
High Speed ◽  
Supply Voltage ◽  
Dispersion Compensation ◽  
Wide Band ◽  
Cmos Technology ◽  
Limiting Factor ◽  
Flip Flop ◽  
Current Output

Inter symbol interference (ISI) caused by dispersion in optical fibers is the major limiting factor on the achievable data rate or transmission distance in high-speed fiber-optic interconnects1. Compared with optical-domain and other electrical-domain dispersion compensation methods, duobinary coding technology is used due to its higher spectral efficiency. In this paper, a monolithically integrated duobinary optical transmitter has be designed and fabricated in standard 0.18 μm CMOS technology. This transmitter consists of a duobinary encoder and a VCSEL driver. The master-slave D flip-flop structure is used to generate the wideband one bit delay which is important for the realization of duobinary signal. An open drain structure is used in VCSEL driver design to provide the higher current output in low supply voltage condition. This duobinary transmitter can operate up to 5 Gb/s with 20 mA current output. The current consumption is only 50 mA under 1.8 V supply voltage.

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